search for: istwoaddress

Can someone explain the Constraints system in X86*.td? For example: let Constraints = "$src1 = $dst" This replaces isTwoAddress (according to svn logs), which I gather is how two-address instructions used to be marked for X86. Except isTwoAddress is still used in X86InstInfo.td. So what gives? What do these two properties actually do? -Dave

On Jun 17, 2008, at 1:36 PM, David Greene wrote: > Can someone explain the Constraints system in X86*.td? > > For example: > > let Constraints = "$src1 = $dst" > > This replaces isTwoAddress (according to svn logs), which I gather > is how > two-address instructions used to be marked for X86. You're right. This is the same as isTwoAddress, just more flexible. > > > Except isTwoAddress is still used in X86InstInfo.td. Because I haven't replaced all uses of is...

On Wednesday 18 June 2008 01:30, Evan Cheng wrote: > On Jun 17, 2008, at 1:36 PM, David Greene wrote: > > Can someone explain the Constraints system in X86*.td? > > > > For example: > > > > let Constraints = "$src1 = $dst" > > > > This replaces isTwoAddress (according to svn logs), which I gather > > is how > > two-address instructions used to be marked for X86. > > You're right. This is the same as isTwoAddress, just more flexible. Ok, but what are the implications for the rest of llvm? What does this constrait say to later ph...

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

I have a question: In the pattern below from X86 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\tdst", [(set GR8:$dst, (add GR8:$src, 1))]>; Since we are emitting only "inc $dst", What makes sure that the $src and $dst are same register? - Sanjiv

..., MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > "inc{b}\tdst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Since we are emitting only "inc $dst", > What makes sure that the $src and $dst are same register? > > - Sanjiv It's enclosed inside : let isTwoAddress = 1 in { ... } (you'll need to scroll up a fair amount to find this). Richard

...gt; "inc{b}\tdst", > > [(set GR8:$dst, (add GR8:$src, 1))]>; > > > > Since we are emitting only "inc $dst", > > What makes sure that the $src and $dst are same register? > > > > - Sanjiv > It's enclosed inside : > > let isTwoAddress = 1 in { > ... > } > > (you'll need to scroll up a fair amount to find this). > That means, it gets converted to dst = src; dst = dst + 1; Right ? - Sanjiv > Richard > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs....

...t;, > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Which seem to have the same restriction that I'm trying to implement, > but I don't understand how this ensures that $src and $dst are the > same register. The trick is that it's nested in this block: let isTwoAddress = 1 in { ... Marking an instruction 'two address' tells the codegen that the first two registers must be constrained to be the same physreg. There is a more general mechanism wih constraints you can also use. -Chris -- http://nondot.org/sabre/ http://llvm.org/

Hi, I am trying to do a backend to a very simple microcontroller. I have some questions. 1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I must declare them like: let isTwoAddress = 1 in def ADD : FopRR< 0b01010, (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), "ADD $sX, $sY"), [(set CPURegs:$sX, (add CPURegs:$isX, CPURegs:$sY))]>; Where CPURegs is my class of register. I suppose that the pass Two...

...[(set GR8:$dst, (add GR8:$src, 1))]>; >>> >>> Since we are emitting only "inc $dst", >>> What makes sure that the $src and $dst are same register? >>> >>> - Sanjiv >>> >> It's enclosed inside : >> >> let isTwoAddress = 1 in { >> ... >> } >> >> (you'll need to scroll up a fair amount to find this). >> >> > That means, it gets converted to > dst = src; > dst = dst + 1; > > Right ? > > - Sanjiv > Yes, I believe the two address instruction pass...

See X86InstrInfo.td let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in def CMOV_GR8 : I<0, Pseudo, This creates a CMOV_GR8 pseudo instruction at isel time which can be expanded during scheduling time. Evan On Dec 10, 2009, at 11:46 AM, Javier Martinez wrote: > Hello, > > My expansion for an operation uses if and loops. How do I...

> >>> > >> It's enclosed inside : > >> > >> let isTwoAddress = 1 in { > >> ... > >> } > >> > >> (you'll need to scroll up a fair amount to find this). > >> > >> > > That means, it gets converted to > > dst = src; > > dst = dst + 1; > > > > Right ? > > > > - Sa...

Hello, My expansion for an operation uses if and loops. How do I introduce branches in the target lowering stage? Do I have to create basic blocks, add the instructions to them and and add them to the machine function's basic block list? Thanks, Javier

...08, at 7:37 AM, Cédric Venet wrote: > Hi, > > I am trying to do a backend to a very simple microcontroller. I have > some > questions. Ok. > 1) I have instruction which do "r1 <- r1 op r2", from what I have > ssen I > must declare them like: > > let isTwoAddress = 1 in > def ADD : FopRR< 0b01010, > (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), > "ADD $sX, $sY"), > [(set CPURegs:$sX, (add CPURegs:$isX, CPURegs: > $sY))]>; > > Where CPURegs is my class of regi...

Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the

...gt; OP= Y and increment operators) - let's see how tblgen will perform. tblgen treats "updating" or "two-address" instructions as if they were three-address instructions, then uses the register allocator to pin the first two operands to the same register. See use of 'isTwoAddress' in the X86 or PPC backends for examples. >>> Why? As far as I understand, LLVM uses BURG/IBURG for instruction >>> selection and both of these tools support costs, AFAIK. >> >> Nope, it uses neither. It uses custom code built into tblgen. > > OK. Now I un...

On Sep 23, 2008, at 9:05 AM, Sanjiv.Gupta at microchip.com wrote: >>>>> >>>> It's enclosed inside : >>>> >>>> let isTwoAddress = 1 in { >>>> ... >>>> } >>>> >>>> (you'll need to scroll up a fair amount to find this). >>>> >>>> >>> That means, it gets converted to >>> dst = src; >>> dst = dst + 1; >>> >>>...

Indeed, i've marked it as commutable: let isCommutable = 1, isTwoAddress = 1 in def XORRdRr : FRdRr<0b0010, 0b01, (outs GPR8:$dst), (ins GPR8:$src1, GPR8:$src2), "xor\t$dst, $src2", [(set GPR8:$dst, (xor GPR8:$src1, GPR8:$src2))]>; -------------- next part...

Hello > and as the return value. Is this a missed optimization from LLVM or did i > miss something out? > Changing the register allocation order didnt work. What are the patterns for xor / mov ? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

I have some instructions that use a register as both an input and as the output. Is there a way to specify this constraint in the InstrInfo.td or will this have to be custom selected/lowered? Thanks -- Christopher Lamb christopher.lamb at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL: