llvm dev - May 2005 - [LLVMdev] avoid live range overlap of "vector" registers

a "vector" register r0 is composed of four 32-bit floating scalar
registers, r0.x, r0.y, r0.z, r0.w.

each scalar reg can be assigned individually, e.g. 

  mov r0.x, r1.y
  add r0.y, r1,x, r2.z
  
or assigned simultaneously with vector instructions, e.g.

  add r0.xyzw, r1.xzyw, r2.xyzw
  
My question is how to define the register in .td file to avoid the
code generator overlaps the live ranges of vector registers?

i could define a 'definition' for each scalar register, but it's
tedious:


class FooReg<string n> : Register<n> {}

def r0_x: FooReg<"r0.x">;
def r0_y: FooReg<"r0.y">;
def r0_z: FooReg<"r0.z">;
def r0_w: FooReg<"r0.w">;
def r1_x: FooReg<"r1.x">;
def r1_y: FooReg<"r1.y">;
def r1_z: FooReg<"r1.z">;
def r1_w: FooReg<"r1.w">;
...

and there are 32 vector registers!


i've read Target.rd:

// RegisterGroup - This can be used to define instances of Register which
// need to specify aliases.
// List "aliases" specifies which registers are aliased to this one. 
This
// allows the code generator to be careful not to put two values with 
// overlapping live ranges into registers which alias.
class RegisterGroup<string n, list<Register> aliases> :
Register<n> {
  let Aliases = aliases;
}


but RegisterGroup seems not to be what I need.

On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> a "vector" register r0 is composed of four 32-bit floating scalar
> registers, r0.x, r0.y, r0.z, r0.w.
>
> each scalar reg can be assigned individually, e.g.
>
>  mov r0.x, r1.y
>  add r0.y, r1,x, r2.z
>
> or assigned simultaneously with vector instructions, e.g.
>
>  add r0.xyzw, r1.xzyw, r2.xyzw
>
> My question is how to define the register in .td file to avoid the
> code generator overlaps the live ranges of vector registers?
If you want to access each part individually, I would suggest doing the 
tedious thing and including them all.  The IA64 backend has 3*128 
registers, so there is precedent for this...

-Chris
> i could define a 'definition' for each scalar register, but
it's tedious:
>
>
> class FooReg<string n> : Register<n> {}
>
> def r0_x: FooReg<"r0.x">;
> def r0_y: FooReg<"r0.y">;
> def r0_z: FooReg<"r0.z">;
> def r0_w: FooReg<"r0.w">;
> def r1_x: FooReg<"r1.x">;
> def r1_y: FooReg<"r1.y">;
> def r1_z: FooReg<"r1.z">;
> def r1_w: FooReg<"r1.w">;
> ...
>
> and there are 32 vector registers!
>
>
> i've read Target.rd:
>
> // RegisterGroup - This can be used to define instances of Register which
> // need to specify aliases.
> // List "aliases" specifies which registers are aliased to this
one.  This
> // allows the code generator to be careful not to put two values with
> // overlapping live ranges into registers which alias.
> class RegisterGroup<string n, list<Register> aliases> :
Register<n> {
>  let Aliases = aliases;
> }
>
>
> but RegisterGroup seems not to be what I need.
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev
>
-Chris

-- 
http://nondot.org/sabre/
http://llvm.cs.uiuc.edu/

Chris Lattner wrote:
> On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> 
>> a "vector" register r0 is composed of four 32-bit floating
scalar
>> registers, r0.x, r0.y, r0.z, r0.w.
>>
>> each scalar reg can be assigned individually, e.g.
>>
>>  mov r0.x, r1.y
>>  add r0.y, r1,x, r2.z
>>
>> or assigned simultaneously with vector instructions, e.g.
>>
>>  add r0.xyzw, r1.xzyw, r2.xyzw
>>
>> My question is how to define the register in .td file to avoid the
>> code generator overlaps the live ranges of vector registers?
> 
> If you want to access each part individually, I would suggest doing the 
> tedious thing and including them all.  The IA64 backend has 3*128 
> registers, so there is precedent for this...
Actually, I think it would be better to define the registers as a machine value
type for packed float x4, and providing
some 'extract' and 'inject' instructions to access individual
components... There should also be a 'shuffle' instruction
(corresponding to the SSE PSHUF instruction) to change the individual components
around.

m.

On  Tue May 10 2005, Chris Lattner wrote:
>On Tue, 10 May 2005, Morten Ofstad wrote:
>> Actually, I think it would be better to define the registers as a
machine
>> value type for packed float x4, and providing some 'extract'
and 'inject'
>> instructions to access individual components... There should also be a 
>> 'shuffle' instruction (corresponding to the SSE PSHUF
instruction) to change
>> the individual components around.
>
>You're right, that would be a better way to go.  To start, I would
suggest
>adding extract/inject intrinsics (not instructions) because it is easier. 
>If you're interested in doing this, there is documentation for this
here:
quote <http://llvm.cs.uiuc.edu/docs/LangRef.html#intrinsics>:
"To do this, extend the default implementation of the
IntrinsicLowering class to handle the intrinsic. Code generators use
this class to lower intrinsics they do not understand to raw LLVM
instructions that they do."

but to which llvm instructions should the extract/inject (or
shuffle/pack) intrinsics be lowered? llvm instruction does not allow
to access the individual scalar value in a packed value.