Displaying 3 results from an estimated 3 matches for "xzyw".
Did you mean:
xyzw
2005 May 06
3
[LLVMdev] avoid live range overlap of "vector" registers
a "vector" register r0 is composed of four 32-bit floating scalar
registers, r0.x, r0.y, r0.z, r0.w.
each scalar reg can be assigned individually, e.g.
mov r0.x, r1.y
add r0.y, r1,x, r2.z
or assigned simultaneously with vector instructions, e.g.
add r0.xyzw, r1.xzyw, r2.xyzw
My question is how to define the register in .td file to avoid the
code generator overlaps the live ranges of vector registers?
i could define a 'definition' for each scalar register, but it's tedious:
class FooReg<string n> : Register<n> {}
def r0_x: FooReg&...
2005 May 10
0
[LLVMdev] avoid live range overlap of "vector" registers
...ster r0 is composed of four 32-bit floating scalar
> registers, r0.x, r0.y, r0.z, r0.w.
>
> each scalar reg can be assigned individually, e.g.
>
> mov r0.x, r1.y
> add r0.y, r1,x, r2.z
>
> or assigned simultaneously with vector instructions, e.g.
>
> add r0.xyzw, r1.xzyw, r2.xyzw
>
> My question is how to define the register in .td file to avoid the
> code generator overlaps the live ranges of vector registers?
If you want to access each part individually, I would suggest doing the
tedious thing and including them all. The IA64 backend has 3*128
regist...
2005 May 10
1
[LLVMdev] avoid live range overlap of "vector" registers
...ing scalar
>> registers, r0.x, r0.y, r0.z, r0.w.
>>
>> each scalar reg can be assigned individually, e.g.
>>
>> mov r0.x, r1.y
>> add r0.y, r1,x, r2.z
>>
>> or assigned simultaneously with vector instructions, e.g.
>>
>> add r0.xyzw, r1.xzyw, r2.xyzw
>>
>> My question is how to define the register in .td file to avoid the
>> code generator overlaps the live ranges of vector registers?
>
> If you want to access each part individually, I would suggest doing the
> tedious thing and including them all. The IA6...