search for: tzu

...es in a table called "categories". Every row has a "parent" field to note if the entry is the sub-category of another (never goes deeper than 1 level). So there might be something like this: id | name | parent 1 Dog 0 2 Pug 1 3 Siamese 5 4 Shih Tzu 1 5 Cat 0 6 Wiener Dog 1 7 Persian 5 I''d like to list it like Dog --Pug --Shih Tzu --Wiener Dog Cat --Siamese --Persian Right now it''s only listing them in one long list. But I''d like to list each parent category and have the subcats listed...

Hi John, I run my pass this way: opt -mypass <input.bc >output.bc So I think "input.bc" is what I should expect, right? Thanks, Jack On Tue, Nov 18, 2008 at 10:23 AM, John Criswell <criswell at cs.uiuc.edu>wrote: > Jack Tzu-Han Hung wrote: > > Hi all, > > > > I'm writing my own pass and use "opt" to launch it. In my pass, I'd like > to see the name of the module I'm working on, so I use > getModuleIdentifier(), trying to get the name such as "test.bc." But the &g...

...ng to implement a dependency analysis pass for machine code block. the result will be returned in a boost graph (http://www.boost.org/libs/graph/doc/table_of_contents.html). just to check if it has already been implemented. it seems to be a very common used pass (for instruction scheduling). -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

The BGL (Boost Graph Library) defines tie(), which is exactly what the tie() defined in STLExtras.h. The header files of GBL use boost::tie(), and other boost libraries use boost::tie() too. How to resolve the ambiguity for compiler? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...e register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

2005/7/26, Chris Lattner <sabre at nondot.org>: > Tzu-Chien Chiu wrote: > > The same problem exists when there are two types of costant registers, > > floating point and integer, and each is declared 'packed' ([4xfloat] > > and [4xint]). The instruction selector doesn't know which instruction > > it should produce b...

...alysisUsage(AU); } class RegAllocMultibank : public MachineFunctionPass { virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired<LiveIntervals>(); AU.addRequired<DependenceAnalyzer>(); MachineFunctionPass::getAnalysisUsage(AU); } }; -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

http://portal.acm.org/citation.cfm?id=75700 On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know if there is any plan or existing work to add a Aho's > > trig language like code generator generator? > > Trig is a code generator generator? Is there any documentation for it > available anywhere? > > -Chris > > &g...

...but it makes the implementing the instruction selector very diffifult. in this example, llvm.select() and llvm.sature() are encountered frist (bootm-up), but they must be 'remembered' and the instruction cannot be generated (BuildMI) until the opcode is known. Which one should I do? -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...n) { ... // perform a final pass over the instructions and compute spill // weights, coalesce virtual registers and remove identity moves but the data structure LiveVariables::VirtRegInfo is _not_ updated. That is, VarInfo::DefInstr may point to an invalid (being coalesced) instruction. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

Actually the problems that Tzu-Chien Chiu are encountering are similar to what should be done for generating SSE code in the X86 backend and also other SIMD instruction sets. I think LLVM neeeds to add instructions for permuting components, extracting and injecting elements in packed types. If the architecture has instructions...

...ot;? The header files in boost do not use fully-qualified tie(). I probably should not modify them. But my .cpp file #include them. I hope I could "using namespace" boost and llvm in .cpp file, because it's tedious to use fully-qualified identifiers in boost and llvm namespace. -- Tzu-Chien Chiu, 3D Graphics Hardware Architect <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...t value may be stored in a constant register, and it's defined _before_ the program starts by API. For example: SetConstantValue( 5, Vector4( 1, 2, 3, 4 ); // C5 = <1,2,3,4> HANDLE handle = LoadCodeFromFile( filename ); SetCode( handle ); // C5 is referenced here Execute(); -- Tzu-Chien Chiu, 3D Graphics Hardware Enginner, <URL:http://www.csie.nctu.edu.tw/~jwchiu>

...code generation libraries. at present i give me preferrence to "Prop": http://www.cs.nyu.edu/leunga/www/prop.html and it's portable too. are there any other good library you could recommend? On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > > http://portal.acm.org/citation.cfm?id=75700 > > Oh, tWig. :) Yes, tree pattern matching is exactly the direction we are > heading. We are slowly making the code generators more and more > automatically generated as time goes on. The SelectionDAG infrastr...

On Mon, 2005-09-05 at 14:45 +0800, Tzu-Chien Chiu wrote: > why there is no general dependency analysis for the "machin code"? > perhaps it's because the instruction scheduling is only implemented > for sparcv9? Most backends use the SelectionDAG infastructure to do this kind of thing. (Simplifying things a bit)...

...CMPfrarr, // 27 CMPfrraa, // 28 CMPfrrar, // 29 CMPfrrra, // 30 CMPfrrrr, // 31 Somewhere in my code, I have to write: unsigned opcode = MI->getOpcode(); // MachineInstr* if (CMPfaaaa == opcode || CMPfaaar == opcode || CMPfaara == opcode || ... -- Tzu-Chien Chiu - XGI Technology, Inc. URL: http://www.csie.nctu.edu.tw/~jwchiu/

...; for all operands. I cannot distinguish between GeneralPurposeRC, INT_ReadOnlyRC, FP_ReadOnlyRC. But a correct register class is necessary for SSARegMap to create a virtual register. 2005/7/22, Misha Brukman <brukman at cs.uiuc.edu>: > On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > > I' have three set of registers - read-only regs, general purpose regs > > (read and write), and write-only regs. How should I partition them > > into different RegisterClasses so that I can easy define the > > instruction? > [snip] > > de...

i'd like to know if there is any plan or existing work to add a Aho's trig language like code generator generator? "...If you are starting a new port, we recommend that you write the instruction selector using the SelectionDAG infrastructure." any other things i should know before i write one? thank you.

...on combining. at present these low-level optimization passes/modules must be implementation ad hoc for each target. there is no low-level target-independent optimization passes. please correct me if i am wrong. On 4/25/05, Chris Lattner <sabre at nondot.org> wrote: > On Mon, 25 Apr 2005, Tzu-Chien Chiu wrote: > > i'd like to know what progress you guys have made (not on cvs?). > > Everything is in CVS. Noone is currently working on automating the > pattern matching generator process yet. Before doing that, there are a > few changes we want to make to the Select...

On Tue, 13 Dec 2005, Tzu-Chien Chiu wrote: > In my ISA, some registers are write-only. These registers serve as > output ports, writing to these registers will output the values to an > external device. They cannot be read. So their live intervals should > not be joined with any other registers. Ok. Since th...