On Tue, 18 Jan 2005, John Cortes wrote:>> Can you say a little bit about MACH-SUIF? With a brief google search, I >> didn't turn up anything that described the architecture. Is it a RISC-like >> machine with 32-bit instruction words? >> > > It's another VM representation. I haven't really gotten to know the nitty > gritty of the language so I'm not too confortable with it, but these two > links should decribe the project. It's based on the work from SUIF. More > specifically, we are using MACHINE-SUIF as a backend to SUIF to generate code > to an embedded processor. We want to move away from using the SUIF frontend, > but the backend works fine. Essentially, for right now, I have to convert > LLVM IR to SUIFvm IR. > > http://www.eecs.harvard.edu/hube/software/nci/suifvm.html > http://www.eecs.harvard.edu/hube/software/nci/overview.htmlOkay, it's a RISCy architecture of sorts. I don't see any documentation on the binary format. Does it require register allocation? If not, it might be easier to write the target in the style of the C-backend (which doesn't use any of the code generator components). If it does, making use of the code generator infrastructure would make sense. -Chris -- http://nondot.org/sabre/ http://llvm.cs.uiuc.edu/
Chris Lattner wrote:> On Tue, 18 Jan 2005, John Cortes wrote: > >>> Can you say a little bit about MACH-SUIF? With a brief google >>> search, I didn't turn up anything that described the architecture. >>> Is it a RISC-like machine with 32-bit instruction words? >>> >> >> It's another VM representation. I haven't really gotten to know the >> nitty gritty of the language so I'm not too confortable with it, but >> these two links should decribe the project. It's based on the work >> from SUIF. More specifically, we are using MACHINE-SUIF as a backend >> to SUIF to generate code to an embedded processor. We want to move >> away from using the SUIF frontend, but the backend works fine. >> Essentially, for right now, I have to convert LLVM IR to SUIFvm IR. >> >> http://www.eecs.harvard.edu/hube/software/nci/suifvm.html >> http://www.eecs.harvard.edu/hube/software/nci/overview.html > > > Okay, it's a RISCy architecture of sorts. I don't see any documentation > on the binary format. Does it require register allocation? If not, it > might be easier to write the target in the style of the C-backend (which > doesn't use any of the code generator components). If it does, making > use of the code generator infrastructure would make sense. > > -Chris >Sample from SUIF disassembler (done by someone else): lda $vr10.p32 <- main.A cvt $vr11.p32 <- $vr10.p32 add $vr12.p32 <- $vr11.p32,$vr9.s32 lod $vr13.s32 <- 0($vr12.p32) cvt $vr8.s32 <- $vr13.s32 mul $vr6.s32 <- $vr7.s32,$vr8.s32 ldc $vr15.s32 <- 5 ldc $vr18.s32 <- 1 add $vr17.s32 <- main.i,$vr18.s32 ******************** So I guess it is RISK. Lots of virtual registers, so I guess allocation isn't a big problem. So you think the C-backend code should be able to output into SUIFvm bytecode? I'm going to look at the main SUIF site for documentation for generating the bytecode, since the MACHINE-SUIF site seems to be lacking. Thanks for the help so far, John
On Wed, 19 Jan 2005, John Cortes wrote:> Sample from SUIF disassembler (done by someone else): > lda $vr10.p32 <- main.A > cvt $vr11.p32 <- $vr10.p32 > add $vr12.p32 <- $vr11.p32,$vr9.s32 > lod $vr13.s32 <- 0($vr12.p32) > cvt $vr8.s32 <- $vr13.s32 > mul $vr6.s32 <- $vr7.s32,$vr8.s32 > ldc $vr15.s32 <- 5 > ldc $vr18.s32 <- 1 > add $vr17.s32 <- main.i,$vr18.s32 > ******************** > > So I guess it is RISK. Lots of virtual registers, so I guess allocation > isn't a big problem. So you think the C-backend code should be able to > output into SUIFvm bytecode? I'm going to look at the main SUIF site for > documentation for generating the bytecode, since the MACHINE-SUIF site seems > to be lacking.Is it "lots" or "infinite"? If it's "lots" you'll still have to do register allocation. If not, use a special purpose pass (like the C writer does) would make sense. -Chris -- http://nondot.org/sabre/ http://llvm.cs.uiuc.edu/