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Dear friends, I have been using the SUIF Machine infrastructure for sometime. Some optimizations are available without using a target machine, i.e. at the SUIFvm level. At this level you have "infinite" registers. Other optimizations, including analyses as for profiling require the use of a target library, a complete backend. It is very sad, that they have discontinued their MIPS backend years ago, and only Alpha, and backends for the ugly x86...

Nikolaos Kavvadias wrote: > Dear friends, > > I have been using the SUIF Machine infrastructure for sometime. Some > optimizations are available without using a target machine, i.e. at the > SUIFvm level. At this level you have "infinite" registers. Other > optimizations, including analyses as for profiling require the use of a > target library, a complete backend. It is very sad, that they have > discontinued their MIPS backend years ago, and only Alpha, and backends &...

On Thu, Jan 20, 2005 at 02:38:39AM -0800, John Cortes wrote: > I tried including the SUIFvm header files and got more errors than I > bargained for. Looks like it hasn't been updated to be portable. I > need some help in getting these suifvm references into the code I'm > writing. While I understand that your current goal is translating LLVM -> SUIF, it seems that y...

...ased on the work from SUIF. More > specifically, we are using MACHINE-SUIF as a backend to SUIF to generate code > to an embedded processor. We want to move away from using the SUIF frontend, > but the backend works fine. Essentially, for right now, I have to convert > LLVM IR to SUIFvm IR. > > http://www.eecs.harvard.edu/hube/software/nci/suifvm.html > http://www.eecs.harvard.edu/hube/software/nci/overview.html Okay, it's a RISCy architecture of sorts. I don't see any documentation on the binary format. Does it require register allocation? If not, it might...

...>> from SUIF. More specifically, we are using MACHINE-SUIF as a backend >> to SUIF to generate code to an embedded processor. We want to move >> away from using the SUIF frontend, but the backend works fine. >> Essentially, for right now, I have to convert LLVM IR to SUIFvm IR. >> >> http://www.eecs.harvard.edu/hube/software/nci/suifvm.html >> http://www.eecs.harvard.edu/hube/software/nci/overview.html > > > Okay, it's a RISCy architecture of sorts. I don't see any documentation > on the binary format. Does it require registe...

...project. It's based on the work from SUIF. More specifically, we are using MACHINE-SUIF as a backend to SUIF to generate code to an embedded processor. We want to move away from using the SUIF frontend, but the backend works fine. Essentially, for right now, I have to convert LLVM IR to SUIFvm IR. http://www.eecs.harvard.edu/hube/software/nci/suifvm.html http://www.eecs.harvard.edu/hube/software/nci/overview.html > -Chris > - John

...question on the LLVM internals. Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled assembly) prior register allocation? Does LLVM use infinite (virtual) registers similar to MachSUIF? This is, of course, meant for a given target in contrast to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is possible at this point. Plus: How do things progress towards LLVM following release. Is Oct 31, a probable date for the release? What about LLVM-TV, is it going to be included. Nikolaos Kavvadias <nkavv-at-physics-dot-auth-dot-gr>

On Tue, 18 Jan 2005, John Cortes wrote: > Hi Chris, Hi! I'm CC'ing the llvmdev list for the benefit of others. > Since I see you're very involved in LLVM, I need a little guidance on getting > from C to MACH-SUIF. > > I've been given the task of using LLVM to translate C code to another VM > architecture known as MACH-SUIF. For this architecture, i don't