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...d (which > doesn't use any of the code generator components). If it does, making > use of the code generator infrastructure would make sense. > > -Chris > Sample from SUIF disassembler (done by someone else): lda $vr10.p32 <- main.A cvt $vr11.p32 <- $vr10.p32 add $vr12.p32 <- $vr11.p32,$vr9.s32 lod $vr13.s32 <- 0($vr12.p32) cvt $vr8.s32 <- $vr13.s32 mul $vr6.s32 <- $vr7.s32,$vr8.s32 ldc $vr15.s32 <- 5 ldc $vr18.s32 <- 1 add $vr17.s32 <- main.i,$vr18.s32 ******************** So I guess it is RISK. Lots of virtual registers, so I guess...

On Tue, 18 Jan 2005, John Cortes wrote: >> Can you say a little bit about MACH-SUIF? With a brief google search, I >> didn't turn up anything that described the architecture. Is it a RISC-like >> machine with 32-bit instruction words? >> > > It's another VM representation. I haven't really gotten to know the nitty > gritty of the language so

...perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0; mem:LD4[<unknown>]   I checked for memoperands for this MachInst, which are not empty, as "has_empty()" returns false. When I check "Value *", pointed by memoperands_begin() and memoperands_end(), i get NULL value. Thus, I don't...