Alexandre Courbot
2016-Jan-15 02:53 UTC
[Nouveau] [PATCH] ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait
Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit of the CTRL1 register instead of writing it entirely in gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also be modified to wait on that single bit only, otherwise a timeout may occur if some other bit of that register is set. This happened at least on GM206 when running glmark2-drm. While we are at it, use the more compact nvkm_wait_msec() to wait for the bit to clear. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/ltc/gm107.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drm/nouveau/nvkm/subdev/ltc/gm107.c index 2af1f9e100fc..47c4e715370f 100644 --- a/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -43,10 +43,8 @@ gm107_ltc_cbc_wait(struct nvkm_ltc *ltc) for (c = 0; c < ltc->ltc_nr; c++) { for (s = 0; s < ltc->lts_nr; s++) { const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200); - nvkm_msec(device, 2000, - if (!nvkm_rd32(device, addr)) - break; - ); + nvkm_wait_msec(device, 2000, addr, + 0x00000004, 0x00000000); } } } -- 2.7.0