Displaying 20 results from an estimated 137 matches for "ltc".
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2015 Sep 03
3
[PATCH 0/3] New instmem implementation for Tegra
...hese
to perform any needed synchronization, and use direct CPU accesses. For Tegra,
provided that we use a write-combined CPU mapping, we just need to make sure the
GPU L2 cache is flushed before we access instobjs and invalidated after.
This patch series first introduces flush/invalidate hooks on LTC so we can
manage the L2 ourselves, and an implementation for GF100+ GPUs. The last patch
then changes GK20A's instmem implementation to use CPU mappings and manage the
GPU L2 in the new acquire/release hooks.
This results in a lot of L2 operations, but thankfully flushing/invalidating an
empty...
2015 Sep 03
2
[PATCH 2/3] ltc/gf100: add flush/invalidate functions
...rbot at nvidia.com> wrote:
> Allow clients to manually flush and invalidate L2. This will be useful
> for Tegra systems for which we want to write instmem using the CPU.
>
> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
> ---
> drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> drm/nouveau/nvkm/subdev/ltc/gf100.c | 36 +++++++++++++++++++++++++++++++++++
> drm/nouveau/nvkm/subdev/ltc/gk104.c | 2 ++
> drm/nouveau/nvkm/subdev/ltc/gm107.c | 2 ++
> drm/nouveau/nvkm/subdev/ltc/priv.h | 2 ++
> 5 files changed, 43 insertions(+)
>
>...
2015 Sep 03
2
[PATCH 2/3] ltc/gf100: add flush/invalidate functions
...clients to manually flush and invalidate L2. This will be useful
>>> for Tegra systems for which we want to write instmem using the CPU.
>>>
>>> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
>>> ---
>>> drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
>>> drm/nouveau/nvkm/subdev/ltc/gf100.c | 36 +++++++++++++++++++++++++++++++++++
>>> drm/nouveau/nvkm/subdev/ltc/gk104.c | 2 ++
>>> drm/nouveau/nvkm/subdev/ltc/gm107.c | 2 ++
>>> drm/nouveau/nvkm/subdev/ltc/priv.h | 2 ++
>>> 5 f...
2008 Dec 26
3
lm() with same formula but different column/factor combinations in data frame
...*****************************************************************************************************
The data frame TEST1 has four factor columns followed by thirteen
numeric columns defined as :
1) Community, levels: "20232"
2) WT, levels: "B", "E", "M"
3) LTC, levels: "L", "M", "S", "1"
4) UC, levels: "1X1", "2X2"
5) UncDmd: Response variable in the linear model
6-16) M1...M11: Explanatory variables in the linear model
A few sample rows in the data frame are as follows:
> TEST1[1:15,]
Co...
2016 Mar 01
0
[PATCH] ltc/gf100: use more reasonable timeout value
LTC operations timeout was set to 2ms, which may be too low for devices
that run at very low clocks (e.g. GM20B) and trigger timeout messages.
Set the timeout to the default 2s. Also remove the redundant error
messages since nvkm_wait_msec() will already display a warning.
Signed-off-by: Alexandre Co...
2019 Sep 16
0
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...ake the level 2
> > cache work on GP10B, such as the stream ID register that is used when an
> > SMMU is used to translate memory addresses.
> >
> > Signed-off-by: Thierry Reding <treding at nvidia.com>
> > ---
> > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> > .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 +
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++++++++++++++++++
> > .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 +
> >...
2019 Sep 16
1
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...cache work on GP10B, such as the stream ID register that is used when an
> > > SMMU is used to translate memory addresses.
> > >
> > > Signed-off-by: Thierry Reding <treding at nvidia.com>
> > > ---
> > > .../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
> > > .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +-
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 +
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c | 69 +++++++++++++++++++
> > > .../gpu/drm/nouveau/nvkm/subdev/ltc/priv.h...
2016 Jan 15
0
[PATCH] ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait
Patch "ltc/gm107: use nvkm_mask to set cbc_ctrl1" sets the 3rd bit
of the CTRL1 register instead of writing it entirely in
gm107_ltc_cbc_clear(). As a counterpart, gm107_ltc_cbc_wait() must also
be modified to wait on that single bit only, otherwise a timeout may
occur if some other bit of that register...
2019 Sep 16
15
[PATCH 00/11] drm/nouveau: Enable GP10B by default
...initialization if already attached
drm/nouveau: tegra: Fall back to 32-bit DMA mask without IOMMU
arm64: tegra: Enable SMMU for GPU on Tegra186
.../boot/dts/nvidia/tegra186-p2771-0000.dts | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 4 +-
.../drm/nouveau/nvkm/engine/device/tegra.c | 152 +++++++++++-------
.../drm/nouveau/nvkm/subdev/instmem/gk20a.c | 35 ++--
.../gpu/drm/nouveau/nvkm/subdev/ltc/Kbuild | 1 +
.../gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.c |...
2017 Jan 30
2
[PATCH] drm/nouveau: gk20a: Turn instmem lock into mutex
...tmem base;
/* protects vaddr_* and gk20a_instobj::vaddr* */
- spinlock_t lock;
+ struct mutex lock;
/* CPU mappings LRU */
unsigned int vaddr_use;
@@ -184,11 +184,10 @@ gk20a_instobj_acquire_iommu(struct nvkm_memory *memory)
struct gk20a_instmem *imem = node->base.imem;
struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
const u64 size = nvkm_memory_size(memory);
- unsigned long flags;
nvkm_ltc_flush(ltc);
- spin_lock_irqsave(&imem->lock, flags);
+ mutex_lock(&imem->lock);
if (node->base.vaddr) {
if (!node->use_cpt) {
@@ -216,7 +215,7 @@...
2016 Feb 20
0
[PATCH v4 3/6] iccsense: implement for ina209, ina219 and ina3221
...ase.c
index a239e49..2536890 100644
--- a/drm/nouveau/nvkm/engine/device/base.c
+++ b/drm/nouveau/nvkm/engine/device/base.c
@@ -1347,6 +1347,7 @@ nvc0_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
+ .iccsense = gf100_iccsense_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
@@ -1383,6 +1384,7 @@ nvc1_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
+ .iccsense = gf100_iccsense_new,
.imem = nv50_instmem_new,
.ltc = gf100_ltc_new,
.mc = gf100_mc_new,
@@ -1418,6 +1420,7 @@ nvc3_chipset = {...
2015 Oct 26
2
[PATCH] instmem/gk20a: exclusively acquire instobjs
...instobj::vaddr* */
spinlock_t lock;
+ unsigned long flags;
/* CPU mappings LRU */
unsigned int vaddr_use;
@@ -188,12 +189,11 @@ gk20a_instobj_acquire(struct nvkm_memory *memory)
struct gk20a_instobj *node = gk20a_instobj(memory);
struct gk20a_instmem *imem = node->imem;
struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
- const u64 size = nvkm_memory_size(memory);
- unsigned long flags;
+ u64 size;
nvkm_ltc_flush(ltc);
- spin_lock_irqsave(&imem->lock, flags);
+ spin_lock_irqsave(&imem->lock, imem->flags);
if (node->vaddr) {
/* remove us f...
2019 Dec 09
11
[PATCH v3 0/9] drm/nouveau: Various fixes for GP10B
...: tegra: Set clock rate if not set
drm/nouveau: secboot: Read WPR configuration from GPU registers
drm/nouveau: gp10b: Add custom L2 cache implementation
drm/nouveau: gp10b: Use correct copy engine
.../drm/nouveau/include/nvkm/subdev/fault.h | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 6 +-
.../drm/nouveau/nvkm/engine/device/tegra.c | 24 ++++--
.../gpu/drm/nouveau/nvkm/subdev/fault/Kbuild | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fault/base.c | 2 +-
.../gpu/drm...
2015 Jan 23
1
[PATCH 1/6] make RAM device optional
...tm.c | 3 +++
> drm/nouveau/nv84_fence.c | 7 +++++--
> drm/nouveau/nvkm/engine/device/base.c | 9 ++++++---
> drm/nouveau/nvkm/subdev/clk/base.c | 2 +-
> drm/nouveau/nvkm/subdev/fb/base.c | 26 ++++++++++++++++++--------
> drm/nouveau/nvkm/subdev/ltc/gf100.c | 14 ++++++++++----
> 7 files changed, 51 insertions(+), 19 deletions(-)
>
> diff --git a/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drm/nouveau/nvkm/subdev/ltc/gf100.c
> index 8e7cc62..ceaa104 100644
> --- a/drm/nouveau/nvkm/subdev/ltc/gf100.c
> +++ b/drm/nouveau/nvkm/subde...
2016 Feb 17
0
[PATCH 1/2] power sensor support
...NVKM_SUBDEV_PMU,
NVKM_SUBDEV_VOLT,
+ NVKM_SUBDEV_ICCSENSE,
NVKM_SUBDEV_THERM,
NVKM_SUBDEV_CLK,
@@ -109,6 +110,7 @@ struct nvkm_device {
struct nvkm_gpio *gpio;
struct nvkm_i2c *i2c;
struct nvkm_subdev *ibus;
+ struct nvkm_iccsense *iccsense;
struct nvkm_instmem *imem;
struct nvkm_ltc *ltc;
struct nvkm_mc *mc;
@@ -164,46 +166,47 @@ struct nvkm_device_quirk {
struct nvkm_device_chip {
const char *name;
- int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
- int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
- int (*bus )(struct nvkm_devic...
2019 Nov 02
13
[PATCH v2 0/9] drm/nouveau: Various fixes for GP10B
...: tegra: Set clock rate if not set
drm/nouveau: secboot: Read WPR configuration from GPU registers
drm/nouveau: gp10b: Add custom L2 cache implementation
drm/nouveau: gp10b: Use correct copy engine
.../drm/nouveau/include/nvkm/subdev/fault.h | 1 +
.../gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 1 +
drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-
.../gpu/drm/nouveau/nvkm/engine/device/base.c | 6 +-
.../drm/nouveau/nvkm/engine/device/tegra.c | 24 ++++--
.../gpu/drm/nouveau/nvkm/subdev/fault/Kbuild | 1 +
.../gpu/drm/nouveau/nvkm/subdev/fault/base.c | 2 +-
.../gpu/drm...
2017 Feb 24
1
[PATCH] drm/nouveau: gk20a: Turn instmem lock into mutex
...t; - spinlock_t lock;
>> + struct mutex lock;
>>
>> /* CPU mappings LRU */
>> unsigned int vaddr_use;
>> @@ -184,11 +184,10 @@ gk20a_instobj_acquire_iommu(struct nvkm_memory *memory)
>> struct gk20a_instmem *imem = node->base.imem;
>> struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
>> const u64 size = nvkm_memory_size(memory);
>> - unsigned long flags;
>>
>> nvkm_ltc_flush(ltc);
>>
>> - spin_lock_irqsave(&imem->lock, flags);
>> + mutex_lock(&imem->lock);
>>
>>...
2017 Aug 31
4
[RFC PATCH] drm/nouveau/therm: initial implementation of new gp1xx temperature sensor
...a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 7bdc7a5ae723..a6221b0996bf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -2166,6 +2166,7 @@ nv130_chipset = {
.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
+ .therm = gp100_therm_new,
.secboot = gm200_secboot_new,
.pci = gp100_pci_new,
.pmu = gp100_pmu_new,
@@ -2200,6 +2201,7 @@ nv132_chipset = {
.ltc = gp100_ltc_new,
.mc = gp100_mc_new,
.mmu = gf100_mmu_new,
+ .therm = gp100_t...
2016 Feb 20
4
[PATCH v3 0/4] Suppor for various power sensors on GF100+
This is a complete rework from the first version I sent out.
Now the implementation is more centered around the power_rails we find in the
SENSE table instead of extdev centered. This makes the implementation a lot
easier and straightforward.
I've added support for the INA219, INA209 and INA3221 sensors found on multiple
Fermi and Kepler cards.
The power consumption is also exported via
2016 Feb 17
3
[PATCH 0/2] Support for INA3221 power sensor
The INA3221 is usually found on mid and high end kepler+ gpus
Marins Patch implements the new iccsense subdev and all needed bits for the
INA3221 power sensor.
My Patch implements the hwmon power1 interface to expose the current power
consumption through hwmon (and can be read out via sysfs or the sensors tool)
Please test these patches for Fermi+ GPUs, that nothing gets messed up and
works as