Displaying 6 results from an estimated 6 matches for "ltc_nr".
2019 Sep 16
0
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...> > +static void
> > +gp10b_ltc_init(struct nvkm_ltc *ltc)
> > +{
> > + struct nvkm_device *device = ltc->subdev.device;
> > +#ifdef CONFIG_IOMMU_API
> > + struct iommu_fwspec *spec;
> > +#endif
> > +
> > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
> > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
> > + nvkm_wr32(device, 0x100800, ltc->ltc_nr);
> > +
> > +#ifdef CONFIG_IOMMU_API
> > + spec = dev_iommu_fwspec_get(device->dev);
> > + if (spec) {
> > + u32 sid = spec->ids[0] & 0xffff;
&g...
2019 Sep 16
1
[PATCH 04/11] drm/nouveau: gp10b: Add custom L2 cache implementation
...p10b_ltc_init(struct nvkm_ltc *ltc)
> > > +{
> > > + struct nvkm_device *device = ltc->subdev.device;
> > > +#ifdef CONFIG_IOMMU_API
> > > + struct iommu_fwspec *spec;
> > > +#endif
> > > +
> > > + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
> > > + nvkm_wr32(device, 0x100800, ltc->ltc_nr);
> > > +
> > > +#ifdef CONFIG_IOMMU_API
> > > + spec = dev_iommu_fwspec_get(device->dev);
> > > + if (spec) {
> > > + u32 sid...
2019 Sep 16
15
[PATCH 00/11] drm/nouveau: Enable GP10B by default
From: Thierry Reding <treding at nvidia.com>
Hi,
the GPU on Jetson TX2 (GP10B) does not work properly on all devices. Why
exactly is not clear, but there are slight differences between the SKUs
that were tested. It turns out that the biggest issue is that on some
devices (e.g. the one that I have), pulsing the GPU reset twice as is
done in the current code (once as part of the power-ungate
2016 Jan 15
0
[PATCH] ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait
...diff --git a/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drm/nouveau/nvkm/subdev/ltc/gm107.c
index 2af1f9e100fc..47c4e715370f 100644
--- a/drm/nouveau/nvkm/subdev/ltc/gm107.c
+++ b/drm/nouveau/nvkm/subdev/ltc/gm107.c
@@ -43,10 +43,8 @@ gm107_ltc_cbc_wait(struct nvkm_ltc *ltc)
for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) {
const u32 addr = 0x14046c + (c * 0x2000) + (s * 0x200);
- nvkm_msec(device, 2000,
- if (!nvkm_rd32(device, addr))
- break;
- );
+ nvkm_wait_msec(device, 2000, addr,
+ 0x00000004, 0x00000000);
}
}
}
--
2.7.0
2019 Nov 02
13
[PATCH v2 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
here's a revised subset of the patches I had sent out a couple of weeks
ago. I've reworked the BAR2 accesses in the way that you had suggested,
which at least for GP10B turned out to be fairly trivial to do. I have
not looked in detail at this for GV11B yet, but a cursory look showed
that BAR2 is accessed in more places, so the
2019 Dec 09
11
[PATCH v3 0/9] drm/nouveau: Various fixes for GP10B
From: Thierry Reding <treding at nvidia.com>
Hi Ben,
here's a revised subset of the patches I had sent out a couple of weeks
ago. I've reworked the BAR2 accesses in the way that you had suggested,
which at least for GP10B turned out to be fairly trivial to do. I have
not looked in detail at this for GV11B yet, but a cursory look showed
that BAR2 is accessed in more places, so the