similar to: [PATCH] ltc/gm107: wait on relevant bit in gm107_ltc_cbc_wait

LTC operations timeout was set to 2ms, which may be too low for devices that run at very low clocks (e.g. GM20B) and trigger timeout messages. Set the timeout to the default 2s. Also remove the redundant error messages since nvkm_wait_msec() will already display a warning. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/subdev/ltc/gf100.c | 8 ++------ 1

Signed-off by: Rosen Penev <rosenp at gmail.com> --- drm/nouveau/dispnv04/disp.h | 4 ++-- drm/nouveau/dispnv04/hw.h | 2 +- drm/nouveau/nouveau_bo.h | 2 +- drm/nouveau/nouveau_display.h | 4 ++-- drm/nouveau/nvkm/engine/dma/user.h | 2 +- drm/nouveau/nvkm/subdev/clk/pll.h | 2 +- drm/nouveau/nvkm/subdev/fb/priv.h | 2 +-

On GM20x and later GPUs, firmware for some essential falcons (notably FECS) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to access certain registers, in a process known as Secure Boot. Secure Boot requires the building of a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure

Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given

Hi all, I have a problem with samba : I can create files, but can't create directories. The server has many shares, on seperated disks. We consider two of them : one 2Tb share and one share with more than 7Tb. Samba configuration is good, and works on many other servers, and on this one except for the large share. Permissions are correctly setted up too. I can read/write files and

Hi all, I have a problem with samba : I can create files, but can't create directories. The server has many shares, on seperated disks. We consider two of them : one 2Tb share and one share with more than 7Tb. Samba configuration is good, and works on many other servers, and on this one except for the large share. Permissions are correctly setted up too. I can read/write files and

Greetings, I have been exploring the use of the caret package to conduct some plsda modeling. Previously, I have come across methods that result in a R2 and Q2 for the model. Using the 'iris' data set, I wanted to see if I could accomplish this with the caret package. I use the following code: library(caret) data(iris) #needed to convert to numeric in order to do regression #I

LTC device is now required for PGRAPH to work, add it. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/engine/device/nve0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c index 54ec53bc6252..cdf9147f32a1 100644 --- a/nvkm/engine/device/nve0.c +++ b/nvkm/engine/device/nve0.c @@ -163,6 +163,7 @@

On 3 September 2015 at 16:42, Alexandre Courbot <acourbot at nvidia.com> wrote: > Allow clients to manually flush and invalidate L2. This will be useful > for Tegra systems for which we want to write instmem using the CPU. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drm/nouveau/include/nvkm/subdev/ltc.h | 1 + >

On 3 September 2015 at 17:13, Alexandre Courbot <gnurou at gmail.com> wrote: > On Thu, Sep 3, 2015 at 4:09 PM, Ben Skeggs <skeggsb at gmail.com> wrote: >> On 3 September 2015 at 16:42, Alexandre Courbot <acourbot at nvidia.com> wrote: >>> Allow clients to manually flush and invalidate L2. This will be useful >>> for Tegra systems for which we want to

On Mon, Sep 16, 2019 at 04:35:30PM +0100, Ben Dooks wrote: > On 16/09/2019 16:04, Thierry Reding wrote: > > From: Thierry Reding <treding at nvidia.com> > > > > There are extra registers that need to be programmed to make the level 2 > > cache work on GP10B, such as the stream ID register that is used when an > > SMMU is used to translate memory addresses.

There is no dedicated instruction for this, so just combine it with the constant offset. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: "10.3" <mesa-stable at lists.freedesktop.org> --- This fixes the spec/glsl-1.50/execution/geometry/dynamic_input_array_index piglit test. src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_gm107.cpp | 5 ++++- 1 file changed,

Spotted by coccinelle: drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c:50:5-8: WARNING: end returns can be simpified Signed-off-by: Martin Peres <martin.peres at free.fr> --- drm/nouveau/nvkm/subdev/fuse/gm107.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/fuse/gm107.c b/drm/nouveau/nvkm/subdev/fuse/gm107.c index ba19158..0b256aa 100644

Hello, The method we previously used on Fermi and Kepler (0x142c) to flush the VBO cache before draw appears to be gone on Maxwell. Is there a replacement method we should use? (Or perhaps that method was never meant for VBO cache flush and instead flushed something related to the vertex quarantine area defined by 0x17bc/0x17c0/0x17c4, which in turn is gone on Maxwell?) Thanks for any light you

Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/fb/gm107.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/fb/gm107.c b/drm/nouveau/nvkm/subdev/fb/gm107.c index 2a91df8..9cc7e61 100644 --- a/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -29,7 +29,7 @@ gm107_fb = { .dtor =

We get 1 warning when build kernel with W=1: drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c:312:1: warning: no previous prototype for 'gm107_gr_init' [-Wmissing-prototypes] In fact, this function is only used in the file in which it is declared and don't need a declaration, but can be made static. so this patch marks this function with 'static'. Signed-off-by: Baoyou Xie

https://bugs.freedesktop.org/show_bug.cgi?id=98391 Bug ID: 98391 Summary: [GM107] priv: HUB0: 614900 00800000 (1d408200) Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau

https://bugs.freedesktop.org/show_bug.cgi?id=103409 Bug ID: 103409 Summary: [GM107] reboot/suspend/lspci hang with nouveau Product: Mesa Version: 17.2 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau

https://bugs.freedesktop.org/show_bug.cgi?id=106662 Bug ID: 106662 Summary: nouveau DPMS poblem with DRI3 (GM107) Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/DRI/nouveau Assignee: nouveau at

So I'm trying to track an special value in IPA instruction generation. https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp#L2561 Register on 0x14 (20) is set to some source on "insn->op == OP_PINTERP" I have found while emulation that such value can be set sometimes to FragCoord.w, I don't however know what that value is and