llvm dev - Jul 2015 - [LLVMdev] prevent an SDValue from lower into an immediate field in load

Hi there,

I am doing relocation in my backend by calling my function getAddrNonPic:

SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG)const{
  SValue Hi=getTarget(N,Ty,DAG, MyBackend::Hi16);
  SValue Lo=getTarget(N,Ty,DAG, MyBackend::Lo16);
  return DAG.getNode(ISD::ADD, DL, Ty,
    DAG.getNode(MyBackend::Hi16, DL, Ty, Hi),
    DAG.getNode(MyBackend::Lo16, DL, Ty, Ho));
}

But sometimes a load instruction is lowered into:

(r2=lo16(symbol))
lw r1, r2(Hi16(symbol))

But what I want is:
(r2=lo16(symbol))
(r3=hi16(symbol))
add r2, r2,r3
lw r1, r2(0)

Can you please show me some hints?

Thanks,
Xiaochu
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On 7/22/2015 1:05 PM, Xiaochu Liu wrote:
>
> But sometimes a load instruction is lowered into:
>
> (r2=lo16(symbol))
> lw r1, r2(Hi16(symbol))
>
> But what I want is:
> (r2=lo16(symbol))
> (r3=hi16(symbol))
> add r2, r2,r3
> lw r1, r2(0)
>
> Can you please show me some hints?
This likely happens during instruction selection, but to make sure, 
could you run your testcase with -mllvm -debug-only=isel? This will show 
all steps of the translation from IR to MIR. You can then narrow down 
the place where this folding happens and take it from there.

-Krzysztof

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