search for: lo16

On Sun, Nov 22, 2015 at 1:28 AM, Rui Ueyama <ruiu at google.com> wrote: > I'm not sure if I understand the semantics of HI16 and LO16 relocations. If > my understanding is correct, a pair of HI16 and LO16 represents an addend > AHL. AHL is computed by (AHI<<16) | (ALO&0xFFFF). Can't we apply HI16 and > LO16 relocations separately and produce the same relocation result? Do we > have to pair them up before...

...t untouched - they are neither read or def:ed. It however seems that Codegen treats subregister definitions as somehow clobbering the whole register. The SSA-code looks like this after isel: (Reg0 and Reg1 are 16bit registers. Reg2, Reg3 and Reg4 are 32 bit registers with 16bit subregs, hi16 and lo16.) Reg0 = #imm0 Reg1 = #imm1 Reg2 = IMPLICIT_DEF Reg3 = INSERT_SUBREG Reg2, Reg0, hi16 Reg4 = INSERT_SUBREG Reg3, Reg1, lo16 After TwoAddressInstructionPass it becomes: Reg5:hi16<def,read-undef> = Reg0 Reg5:lo16<def> = Reg1 So, in my world this means a setting of the high...

If I write %reg16506<def> = INSERT_SUBREG %reg16506, %reg16445, hi16; #1 %reg16506<def> = INSERT_SUBREG %reg16506, %reg16468, lo16; #2 store %reg16506 #3 it will not coalesce, as LiveVariables: on #2: %16506 gets #2 as a kill #3: %16506 gets #3 as an additional kill LiveIntervalAnalysis: The common case of a def/kill in same MBB, is m...

...terfere with each other? See the >> detailed problem description below. > > We do have a limitation in our current liveness tracking for > sub-register. Therefore, I am not sure that is possible. > > Conceptually, what you want is: > Reg5:hi16<def,read-undef> > Reg5:lo16<def,read-undef> > > However, I guess this wouldn’t be supported, because it would mean that > we do not care about the value of hi16 at the definition of Reg5:lo16. > This is true, but after this definition we do care about hi16 and I am > afraid read-undef does not convey the...

On May 19, 2011, at 7:47 AM, Jonas Paulsson wrote: > Hi, > > I am combining 16-bit registers to a 32 bit register in order to make a wide store, as per below: > > 732 %reg16506:hi16<def,dead> = COPY %reg16445<kill>; > 740 %reg16506:lo16<def> = COPY %reg16468<kill>; > 748 %r3<def,dead> = store %reg16506<kill>, %r3, > > As you can see, LiveVariables has marked the high part dead, even though the super-register is used at SlotIndex 748. Why is this? Should I add anything special to the basic BuildMI...

Hi, I am combining 16-bit registers to a 32 bit register in order to make a wide store, as per below: 732 %reg16506:hi16<def,dead> = COPY %reg16445<kill>; 740 %reg16506:lo16<def> = COPY %reg16468<kill>; 748 %r3<def,dead> = store %reg16506<kill>, %r3, As you can see, LiveVariables has marked the high part dead, even though the super-register is used at SlotIndex 748. Why is this? Should I add anything special to the basic BuildMI calls? The Li...

...everal cases where cross class joins are carried out that makes the code turn out illegal, because the "new" register class is not allowed in all instructions where it is now used. For example, by joining %vreg4, %vreg7 and %vreg9 the following code %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 is turned into %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17 aN32_0_7:%vreg4 The load instru...

...t; >> On Sat, Nov 21, 2015 at 9:28 AM, Rui Ueyama <ruiu at google.com> wrote: >> > On Fri, Nov 20, 2015 at 10:13 PM, Simon Atanasyan <simon at atanasyan.com> >> > wrote: >> >> >> >> In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 >> >> relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses >> >> combined addend (AHI << 16) + (short)ALO where AHI is original >> >> R_MIPS_HI16 addend and ALO is addend of the matching R_MIPS_LO16 >> >> relocation [1]. There are tw...

On Sat, Nov 21, 2015 at 9:28 AM, Rui Ueyama <ruiu at google.com> wrote: > On Fri, Nov 20, 2015 at 10:13 PM, Simon Atanasyan <simon at atanasyan.com> > wrote: >> >> In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 >> relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses >> combined addend (AHI << 16) + (short)ALO where AHI is original >> R_MIPS_HI16 addend and ALO is addend of the matching R_MIPS_LO16 >> relocation [1]. There are two methods to do matching and R_MIPS_...

...s joins are carried out that makes > the code turn out illegal, because the "new" register class is not > allowed in all instructions where it is now used. > > For example, by joining %vreg4, %vreg7 and %vreg9 the following code > > %vreg7<def> = COPY %vreg4:lo16; aNl_0_7:%vreg7 aN32_0_7:%vreg4 > %vreg9<def> = COPY %vreg7; rN:%vreg9 aNl_0_7:%vreg7 > %vreg17<def> = load %vreg9<kill>; aN40_0_7:%vreg17 rN:%vreg9 > > is turned into > > %vreg17<def> = load %vreg4:lo16<kill>; aN40_0_7:%vreg17 >...

...y target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> = REG_SEQUENCE %vreg2, hi16, %vreg43, lo16; reg32:%vreg20 hi16:%vreg2 lo16:%vreg43 Becomes 16L %vreg20:hi16<def,undef> = COPY %a2h<kill>, %vreg20<imp-def>; reg32:%vreg20 368L %vreg20:lo16<def> = mov 0, pred:0, pred:...

Hi there, I am doing relocation in my backend by calling my function getAddrNonPic: SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG)const{ SValue Hi=getTarget(N,Ty,DAG, MyBackend::Hi16); SValue Lo=getTarget(N,Ty,DAG, MyBackend::Lo16); return DAG.getNode(ISD::ADD, DL, Ty, DAG.getNode(MyBackend::Hi16, DL, Ty, Hi), DAG.getNode(MyBackend::Lo16, DL, Ty, Ho)); } But sometimes a load instruction is lowered into: (r2=lo16(symbol)) lw r1, r2(Hi16(symbol)) But what I want is: (r2=lo16(symbol)) (r3=hi16(symbol)) add r2, r2,r...

Hi, I am working on support R_MIPS_HI16 / R_MIPS_LO16 in the new LLD and have a couple of questions. == Q1 In case of MIPS O32 ABI we have to find a matching R_MIPS_LO16 relocation to calculate R_MIPS_HI16 one because R_MIPS_HI16 uses combined addend (AHI << 16) + (short)ALO where AHI is original R_MIPS_HI16 addend and ALO is addend of the matc...

...erands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5 >> >> I tried: >> >> def : Pat<(i32 imm:$imm), >> (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>; > > It is possible to write multi-instruction pattern, e.g. > X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? > Sounds like you want to define them as SDNodeXform that returns upper > and lower 16 bits respectively. Take a look at PSxLDQ_imm in >...

...and there may be a more elegant method stmw r31,-4(r1) addi r9,r1,-28 li r31,0xf andc r9,r9,r31 ; for quadword-aligned stack data slwi r6,r6,2 ; adjust for word size slwi r4,r4,2 add r4,r4,r8 ; r4 = data+data_len mfspr r0,256 ; cache old vrsave addis r31,0,hi16(0xfffffc00) ori r31,r31,lo16(0xfffffc00) mtspr 256,r31 ; declare VRs in vrsave cmplw cr0,r8,r4 ; i<data_len bc 4,0,L1400 ; load coefficients into v0-v7 and initial history into v8-v15 li r31,0xf and r31,r8,r31 ; r31: data%4 li r11,16 subf r31,r31,r11 ; r31: 4-(data%4) slwi r31,r31,3 ; convert to bits for vsro li...

...he following live ranges for vreg1954: %vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r And vreg1954 is mentioned in these instructions: 5000B %vreg1954:hi16<def,read-undef> = mv_any16 32766 [...] 5048B mv_ar16_r16_rmod1 %vreg1954:hi16, %vreg1753 5056B %vreg1954:lo16<def> = mv_nimm6_ar16 0 5064B Store40FI %vreg1954, <fi#2> [...] 5128B %vreg223<def> = COPY %vreg1954 [...] 5216B %vreg1178<def> = COPY %vreg1954 [...] 5348B %vreg1955<def> = COPY %vreg1954 Then it tries to rematerialize: Value %vreg1954:0 at 5000r...

+llvmdev -llvmcommits On Fri, Nov 12, 2010 at 8:03 AM, Jim Grosbach <grosbach at apple.com> wrote: > Sorta. getBinaryCodeForInst() is auto-generated by tablegen, so shouldn't be modified directly. The target can register hooks for instruction operands for any special encoding needs, including registering fixups, using the EncoderMethod string. For an example, have a look at the

...tiple machine > instructions from a single pattern? Or do these cases always have > to be > manually expanded? PPC has a bunch of examples, for example: // Arbitrary immediate support. Implement in terms of LIS/ORI. def : Pat<(i32 imm:$imm), (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; // ADD an arbitrary immediate. def : Pat<(add GPRC:$in, imm:$imm), (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>; // OR an arbitrary immediate. def : Pat<(or GPRC:$in, imm:$imm), (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>...

Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC backend, which has the exact same issue > for integer consta...

Are there any examples of using tablegen to generate multiple machine instructions from a single pattern? Or do these cases always have to be manually expanded? -Dave