Hello, I previously sent this message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not :-) . Anyways, here are my primilary reflexions for this new language : http://www.sendspace.com/file/o8tmz0 What are your feedbacks ? PS : Next week, I will be on vacation for 3 mounths, so I may have irregular access to the internet. Cheers, Jonas
Jonas Baggett <jonasb at tranquille.ch> writes:> What are your feedbacks ?Hello Jonas, How is that related to LLVM? I see no references to LLVM on your announcement nor on your document.
Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never used LLVM, I just read a litlle the documentation and the tutorial. Cheers, Jonas Le 30. 08. 13 11:24, Óscar Fuentes a écrit :> Jonas Baggett<jonasb at tranquille.ch> writes: > >> What are your feedbacks ? > Hello Jonas, > > How is that related to LLVM? I see no references to LLVM on your > announcement nor on your document.