search for: myhdl

...ll a écrit : > If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). That's a good idea before I go too far , and I think that MyHDL worths a look too. For Symbolics Processor Designer, I tried to find that in google, but I am not sure that I found what you were speaking about. Do you have a link ? I just discover that this mailing list is for speaking about LLVM developpement and usage only, so for all non LLVM related dis...

...message, but it was in HTML only, so it was unreadable. I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada. I don't know if it is a project that I will abandon as fast as it popped up in my mind, or not :-) . Anyways, here are my primilary reflexions for this new language : http://www.sendspace.com/file/o8tmz0 What are your feedbacks ? PS : Next week, I wil...

If you're designing a new high-level HDL, then it would be a good idea to familiarise yourself with the state of the art in this area (e.g. Bluespec System Verilog, Symbolics Processor Designer, and similar tools). Starting from comparisons to VHDL and Verilog is like designing a new high-level programming language today that is designed to be a better high-level programming language that is

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never