llvm dev - Apr 2013 - [LLVMdev] is there any passes or compiling options that can aviod to generate vector instructions and 'select' instruction in IR

hi guys:
is there any passes or compiling options that can aviod to generate vector
instructions and 'select' instruction in IR.
i think that these instructions can be replaced with other instructions in
LLVM IR. So if there is a way to eliminate these instructions during
compilation?



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Hi,
> is there any passes or compiling options that can aviod to generate vector
> instructions and 'select' instruction in IR.
> i think that these instructions can be replaced with other instructions in
> LLVM IR. So if there is a way to eliminate these instructions during
> compilation?
you can avoid having optimizers create vector instructions by not running
the vectorizer pass.  However select is harder to avoid because it is created
by fundamental optimization passes that you have to run to get good code.
Also, front-ends might create them directly.  Why do you want to avoid
"select"?

Ciao, Duncan.

On 15/04/13 09:55, Duncan Sands wrote:
> Hi,
>
>> is there any passes or compiling options that can aviod to generate
vector
>> instructions and 'select' instruction in IR.
>> i think that these instructions can be replaced with other instructions
in
>> LLVM IR. So if there is a way to eliminate these instructions during
>> compilation?
>
> you can avoid having optimizers create vector instructions by not running
> the vectorizer pass.  However select is harder to avoid because it is
created
> by fundamental optimization passes that you have to run to get good code.
> Also, front-ends might create them directly.  Why do you want to avoid
"select"?
>
A trick I sometimes use is to set the vector width to 1 using '-mllvm 
-force-vector-width=1' as a flag to clang.  That seems to suppress 
vectorization nicely although I guess that there are nicer methods to 
achieve the same effect.

Cheers,
  Roel