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[LLVMdev] is there any passes or compiling options that can aviod to generate vector instructions and 'select' instruction in IR
2013 Apr 14
2
[LLVMdev] is there any passes or compiling options that can aviod to generate vector instructions and 'select' instruction in IR
...ns can be replaced with other instructions in LLVM IR. So if there is a way to eliminate these instructions during compilation? -- View this message in context: http://llvm.1065342.n5.nabble.com/is-there-any-passes-or-compiling-options-that-can-aviod-to-generate-vector-instructions-and-select-iR-tp56730.html Sent from the LLVM - Dev mailing list archive at Nabble.com.