llvm dev - Oct 2012 - [LLVMdev] Predication on SIMD architectures and LLVM

Ralf Karrenberg <Chareos at gmx.de> writes:
> I am sure I've seen some postings on the list concerning architectures
> that support predicated execution and how to map that to LLVM IR, I'm
> just not sure anymore when and who was involved :).
I was one of them.  I suggested adding general predication to the LLVM
IR but that doesn't look like it's going to happen.  Dan Gohman had
another idea on how to represent predicate masks but that also didn't
relaly go anywhere.

None of your proposed solutions is ideal.  We really should have
first-class predication in the IR.  It's only going to get more
important.

                      -David

On 22 Oct 2012, at 18:10, <dag at cray.com> wrote:
> None of your proposed solutions is ideal.  We really should have
> first-class predication in the IR.  It's only going to get more
> important.
Perhaps I am missing something, but isn't a predicated instruction
effectively an single-instruction version of an arithmetic operation followed by
a select?  As we can already represent this in the IR, and already match other
predicated instructions (e.g. on ARM) to this pattern, what is gained by adding
predication directly to the IR?

David

David Chisnall <David.Chisnall at cl.cam.ac.uk> writes:
> Perhaps I am missing something, but isn't a predicated instruction
> effectively an single-instruction version of an arithmetic operation
> followed by a select?  
No, it is not.  Among other things, predication is used to avoid traps.
A vector select is an entirely different operation.
> As we can already represent this in the IR, and already match other
> predicated instructions (e.g. on ARM) to this pattern, what is gained
> by adding predication directly to the IR?
Predicated loads, stores, divides, sqrts, etc. are essential for
correctly vectorizing loops with conditionals due to safety concerns.
If the loop body has no dangerous operations, then yes, a vector select
can be used without problems but it is often slower than predication.
Usually the hardware can optimize instructions with certain values of
predicates.

                              -David