search for: i_select

...owers vector-select instructions to SSE4 and AVX blends. Other targets emulate blends using a sequence of ANDs and Xors. Later today I will fix a few tests (which expect a slightly different output) and enable the '-promote-element' flag by default. [1] http://llvm.org/docs/LangRef.html#i_select [2] https://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?revision=139992 Thanks, Nadav --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of th...

I am talking about the LLVM select instruction, not a vector select: http://llvm.org/docs/LangRef.html#i_select In any non-trapping case, an arithmetic operation (or sequence of operations) followed by a select is semantically equivalent to the predicated version. This is exactly how predicated instructions on ARM are handled. For example, the following IR: %cmp = icmp sgt i32 %c, %b %add = add nsw i...

David Chisnall <David.Chisnall at cl.cam.ac.uk> writes: > Perhaps I am missing something, but isn't a predicated instruction > effectively an single-instruction version of an arithmetic operation > followed by a select? No, it is not. Among other things, predication is used to avoid traps. A vector select is an entirely different operation. > As we can already represent

...ect instructions to SSE4 and AVX blends. Other targets emulate blends using a sequence of ANDs and Xors. > > Later today I will fix a few tests (which expect a slightly different output) and enable the '-promote-element' flag by default. > > [1] http://llvm.org/docs/LangRef.html#i_select > [2] https://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-blend.ll?revision=139992 > > > Thanks, > Nadav > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain co...

David Chisnall <David.Chisnall at cl.cam.ac.uk> writes: > I am talking about the LLVM select instruction, not a vector select: > > http://llvm.org/docs/LangRef.html#i_select That is what I mean by a vector select. > In any non-trapping case, an arithmetic operation (or sequence of > operations) followed by a select is semantically equivalent to the > predicated version. Yes. > Separating the select, which embodies the predication, from the > operat...

On 22 Oct 2012, at 18:10, <dag at cray.com> wrote: > None of your proposed solutions is ideal. We really should have > first-class predication in the IR. It's only going to get more > important. Perhaps I am missing something, but isn't a predicated instruction effectively an single-instruction version of an arithmetic operation followed by a select? As we can already

..." instruction, which is useful for flattening control structures and recognizing idioms like min/max and saturated arithmetic. Currently only the C backend supports it, though full support will be available in LLVM 1.3. Here are the docs: http://llvm.cs.uiuc.edu/docs/LangRef.html#i_select 7. Misha added support to the pass manager for adding 'transitive' relationships between passes. 8. llvm.memset, llvm.memcpy, and llvm.memmove intrinsics were added to LLVM. These allow code generators to produce fast inline code for these functions and for the optimizer to unders...

..." instruction, which is useful for flattening control structures and recognizing idioms like min/max and saturated arithmetic. Currently only the C backend supports it, though full support will be available in LLVM 1.3. Here are the docs: http://llvm.cs.uiuc.edu/docs/LangRef.html#i_select 7. Misha added support to the pass manager for adding 'transitive' relationships between passes. 8. llvm.memset, llvm.memcpy, and llvm.memmove intrinsics were added to LLVM. These allow code generators to produce fast inline code for these functions and for the optimizer to unders...