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add1t
2012 Oct 23
0
[LLVMdev] Predication on SIMD architectures and LLVM
...version. This is exactly how predicated instructions on ARM are handled. For example, the following IR:
%cmp = icmp sgt i32 %c, %b
%add = add nsw i32 %b, 1
%add1 = add nsw i32 %c, 2
%retval.0 = select i1 %cmp, i32 %add, i32 %add1
Becomes this ARM assembly:
add r2, r1, #2
cmp r1, r0
addgt r2, r0, #1
mov r0, r2
An equally valid form would be:
cmp r1, r0
addle r2, r1, #2
addgt r2, r0, #1
mov r0, r2
Separating the select, which embodies the predication, from the operations allows more choice in terms of the final representation. Unless the load or store is volatile, the compil...
2012 Oct 23
0
[LLVMdev] Predication on SIMD architectures and LLVM
On 22 Oct 2012, at 18:10, <dag at cray.com> wrote:
> None of your proposed solutions is ideal. We really should have
> first-class predication in the IR. It's only going to get more
> important.
Perhaps I am missing something, but isn't a predicated instruction effectively an single-instruction version of an arithmetic operation followed by a select? As we can already
2012 Oct 23
2
[LLVMdev] Predication on SIMD architectures and LLVM
David Chisnall <David.Chisnall at cl.cam.ac.uk> writes:
> Perhaps I am missing something, but isn't a predicated instruction
> effectively an single-instruction version of an arithmetic operation
> followed by a select?
No, it is not. Among other things, predication is used to avoid traps.
A vector select is an entirely different operation.
> As we can already represent