Hi all,
I think I found a bug in LLVM 3.0: When compiling for a target without
SSE2 support, there were some 128-bit PXOR instructions in the generated
code.
I traced it down to the following definition in X86InstrSSE.td:
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
[(set FR32:$dst, fp32imm0)]>,
Requires<[HasSSE1]>, TB, OpSize;
I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the
trick. I noticed that TOT has a different definition and I tried
substituting that as well but again no luck. Is there a simple way to
make it work with LLVM 3.0 or should I consider updating to a later version?
Thanks,
Nicolas
On Fri, Jan 20, 2012 at 2:47 PM, Nicolas Capens <nicolas.capens at gmail.com> wrote:> Hi all, > > I think I found a bug in LLVM 3.0: When compiling for a target without > SSE2 support, there were some 128-bit PXOR instructions in the generated > code. > > I traced it down to the following definition in X86InstrSSE.td: > > def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", > [(set FR32:$dst, fp32imm0)]>, > Requires<[HasSSE1]>, TB, OpSize; > > I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the > trick. I noticed that TOT has a different definition and I tried > substituting that as well but again no luck. Is there a simple way to > make it work with LLVM 3.0 or should I consider updating to a later version?That particular issue doesn't look familiar; if you can reproduce with trunk, please file a bug report. -Eli
I suspect this would have been fixed by r*143996*. Though that wasn't the intention of that commit based on the commit comments. On Fri, Jan 20, 2012 at 2:55 PM, Eli Friedman <eli.friedman at gmail.com>wrote:> On Fri, Jan 20, 2012 at 2:47 PM, Nicolas Capens > <nicolas.capens at gmail.com> wrote: > > Hi all, > > > > I think I found a bug in LLVM 3.0: When compiling for a target without > > SSE2 support, there were some 128-bit PXOR instructions in the generated > > code. > > > > I traced it down to the following definition in X86InstrSSE.td: > > > > def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", > > [(set FR32:$dst, fp32imm0)]>, > > Requires<[HasSSE1]>, TB, OpSize; > > > > I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the > > trick. I noticed that TOT has a different definition and I tried > > substituting that as well but again no luck. Is there a simple way to > > make it work with LLVM 3.0 or should I consider updating to a later > version? > > That particular issue doesn't look familiar; if you can reproduce with > trunk, please file a bug report. > > -Eli > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120120/bfd661b7/attachment.html>