search for: mrminitreg

Hi all, I think I found a bug in LLVM 3.0: When compiling for a target without SSE2 support, there were some 128-bit PXOR instructions in the generated code. I traced it down to the following definition in X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the trick. I noticed that TOT has a different definition and I tried substit...

Hi, I noticed a bunch of psuedo instructions used for creation of constants without generating loads. e.g. pxor xmm0, xmm0 Here is an example of what i am referring to snipped from X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; My question is why was there a need to define such a pseudo instruction? Wouldn't it be cleaner to use a def: Pat<> which selects: pxor $dst,...

...ote: > Hi all, > > I think I found a bug in LLVM 3.0: When compiling for a target without > SSE2 support, there were some 128-bit PXOR instructions in the generated > code. > > I traced it down to the following definition in X86InstrSSE.td: > >   def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", >                    [(set FR32:$dst, fp32imm0)]>, >                    Requires<[HasSSE1]>, TB, OpSize; > > I tried replacing the HasSSE1 with a HasSSE2 but that didn't do the > trick. I noticed that TOT has a different definition...

...erand& MO = MI.getOperand(i); > - if (MO.isRegister()) { > - unsigned Reg = MO.getReg(); > - if (isX86_64NonExtLowByteReg(Reg)) > - REX |= 0x40; > - } > - } > - > - switch (Desc.TSFlags & X86II::FormMask) { > - case X86II::MRMInitReg: > - if (isX86_64ExtendedReg(MI.getOperand(0))) > - REX |= (1 << 0) | (1 << 2); > - break; > - case X86II::MRMSrcReg: { > - if (isX86_64ExtendedReg(MI.getOperand(0))) > - REX |= 1 << 2; > - i = isTwoAddr ? 2 : 1; > -...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And