Damjan Marion
2011-Jun-22 10:49 UTC
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
Hi, I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. Here is output: # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) Target: arm-unknown-freebsd Thread model: posix "/opt/llvm/bin/clang" -cc1 -triple armv5e-unknown-freebsd -S -disable-free -main-file-name rrx.c -mrelocation-model static -mdisable-fp-elim -mconstructor-aliases -target-abi apcs-gnu -target-cpu arm926ej-s -msoft-float -mfloat-abi soft -target-feature +soft-float -target-feature +soft-float-abi -target-feature -neon -target-linker-version 123.2 -momit-leaf-frame-pointer -v -coverage-file rrx.S -resource-dir /opt/llvm/bin/../lib/clang/3.0 -ferror-limit 19 -fmessage-length 162 -fno-signed-char -fgnu-runtime -fdiagnostics-show-option -fcolor-diagnostics -o rrx.S -x c rrx.c clang -cc1 version 3.0 based upon llvm 3.0svn hosted on x86_64-apple-darwin10.7.0 #include "..." search starts here: #include <...> search starts here: /opt/llvm/bin/../lib/clang/3.0/include /usr/include End of search list. Code: void bla (long long a) { if (a & ((unsigned long long)1 << 24)) a >>= 1; } generated .S: bla: str r11, [sp, #-4]! mov r11, sp sub sp, sp, #20 bic sp, sp, #7 str r1, [sp, #12] str r0, [sp, #8] ldrb r2, [sp, #11] tst r2, #1 str r0, [sp, #4] str r1, [sp] beq .LBB0_2 b .LBB0_1 .LBB0_1: ldr r0, [sp, #8] ldr r1, [sp, #12] asrs r1, r1, #1 rrx r0, r0 << Thumb-2 instruction str r1, [sp, #12] str r0, [sp, #8] .LBB0_2: mov sp, r11 ldr r11, [sp], #4 bx lr rrx r0,r0 is thumb-2 instruction, however target-cpu is set to arm926ej-s which is ARMv5E architecture and it doesn't support Thumb-2. Is this a known issue? Thanks, Damjan
Anton Korobeynikov
2011-Jun-22 11:13 UTC
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
Hi> I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. > > Here is output: > > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) > Target: arm-unknown-freebsd > Thread model: posix > "/opt/llvm/bin/clang" -cc1 -triple armv5e-unknown-freebsdIt seems you're generating arm, not thumb code. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
Damjan Marion
2011-Jun-22 11:28 UTC
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
On Jun 22, 2011, at 1:13 PM, Anton Korobeynikov wrote:> Hi > >> I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. >> >> Here is output: >> >> # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c >> clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) >> Target: arm-unknown-freebsd >> Thread model: posix >> "/opt/llvm/bin/clang" -cc1 -triple armv5e-unknown-freebsd > It seems you're generating arm, not thumb code.Exactly i want to generate ARM code and I got "RRX r0,r0" which is Thumb-2.
Renato Golin
2011-Jun-22 13:16 UTC
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote:> # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.cEven though you specified cpu as arm9, it's probably generating generic ARM IR (use -emit-llvm -S and see), which defaults to ARM instructions. If you want thumb, use triple = thumb-unknown-freebsd, but still, that will have problems. You can do it in two steps (clang -> IR, llc -> ASM) and specify all options on both steps, or wait until the clang patch for cross-compilation is reviewed and applied. cheers, --renato
Damjan Marion
2011-Jun-22 13:33 UTC
[LLVMdev] ARM thumb-2 instruction used for non-thumb2 CPUs
On Jun 22, 2011, at 3:16 PM, Renato Golin wrote:> On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: >> # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > > Even though you specified cpu as arm9, it's probably generating > generic ARM IR (use -emit-llvm -S and see), which defaults to ARM > instructions. > > If you want thumb, use triple = thumb-unknown-freebsd, but still, that > will have problems. You can do it in two steps (clang -> IR, llc -> > ASM) and specify all options on both steps, or wait until the clang > patch for cross-compilation is reviewed and applied.Hi Renato, I dont want to generate Thumb code, actually i missed in my previous email that "rrx r0,r0" is both ARM and thumb-2 instruction, but only defined in ARMv7. llvm produces "rrx r0,r0" mnemonics for ARMv5 targets, however ARM Architecture Reference Manual for ARMv5 doesn't know about that mnemonics. There is equivalent mnemonics on ARMv5: "mov r0,r0, rrx" both "rrx r0,r0" and "mov r0, r0, rrx" result in same opcode: 0xe1a00060. Problem is that in case when old binutils are used (in my case freebsd is using old one due to license upgrade to GPLv3) AS doesn't understand new mnemonics and fails. Can we change to old mnemonic at least when ARMv4 and ARMv5 code is generated? Thanks,
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