llvm dev - Feb 2011 - [LLVMdev] TableGen syntax for matching a constant load

Hi all,
I'm trying to add a X86 pattern to turn
	movl $-1, %eax
into
	orl $-1, $eax
I can't find a way to express this in TableGen syntax though.

def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>;

results in an assertion about 'Unknown Node'.

Joerg

On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote:
> Hi all,
> I'm trying to add a X86 pattern to turn
> 	movl $-1, %eax
> into
> 	orl $-1, $eax
> I can't find a way to express this in TableGen syntax though.
> 
> def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>;
> 
> results in an assertion about 'Unknown Node'.
Hi Joerg,

This is problematic to define the obvious way because "orl" takes two
inputs and produces an output, but this specific form of it ignores the inputs
and just sets the register (and flags).

We can handle this by defining a new pseudo-op that just defines the
register+flags.  Take a look at how "xor reg,reg" -> "mov 0,
reg"  is done.  MOV32r0 is the place to start: MCInstLowering then turns it
into the actual operation.

-Chris

On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote:
> I'm trying to add a X86 pattern to turn
> 	movl $-1, %eax
> into
> 	orl $-1, $eax
Please make sure to measure the performance impact of doing this. You are
creating a false dependency on the last instruction to write %eax, and the CPU
won't be able to execute the following instructions in parallel.

You may want to consider using xorl+decl instead. It is also three bytes, and
there are no false dependencies. The xor idiom is recognized by processors as
old as Pentium 4 as having no dependencies.

/jakob

On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen
wrote:
> 
> On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote:
> 
> > I'm trying to add a X86 pattern to turn
> > 	movl $-1, %eax
> > into
> > 	orl $-1, $eax
> 
> Please make sure to measure the performance impact of doing this. You
> are creating a false dependency on the last instruction to write %eax,
> and the CPU won't be able to execute the following instructions in
> parallel.
I am primarily interested in size here, not speed.
> You may want to consider using xorl+decl instead. It is also three
> bytes, and there are no false dependencies. The xor idiom is recognized
> by processors as old as Pentium 4 as having no dependencies.
Any examples of how to create more than one instructions for a given
pattern? There are some other cases I could use this for.

Joerg