search for: mov32r0

...u3696"<#1073741833>(d2473,b2486):u2482] s1532: ADJCALLSTACKDOWN64 [d1533<RSP>!(+d3206,\~d3647",u1557):, d1534<EFLAGS>!(+d3206,d1540,):d1533, d1535<SSP>!(+d3206,\~d3646",u1558):d1534, u1536<RSP>!(+d3206):, u1537<SSP>!(+d3206):u1536] s1538: MOV32r0 [d1539<R12D>(+d3202,,):, d1540<EFLAGS>!(d1534,d1549,):, d1541<R12>(+d3202,,u3221):d1539] s1542: MOV32ri64 [d1543<RDX>(+d3206,\~d3645",u1561):d1535] s1544: COPY [d1545<RDI>(+d3206,\~d3644",u1559):d1543, u1546<R13>(d785):] s1547: MOV32r0 [d...

Hi Scott, That #1073741833 is a register mask. They are treated as aggregate registers (essentially sets of registers), so if it includes R9D and R11D, it will be treated as being aliased with both. These separate defs are there because they reach disjoint registers. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott

...re no false dependencies. The xor idiom is recognized >> by processors as old as Pentium 4 as having no dependencies. > > Any examples of how to create more than one instructions for a given > pattern? There are some other cases I could use this for. def : Pat<(i32 -1), (DEC32r (MOV32r0))>; /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110226/2301e286/attachment.html>

On Sat, Feb 26, 2011 at 01:07:39PM -0800, Jakob Stoklund Olesen wrote: > > On Feb 25, 2011, at 7:27 PM, Joerg Sonnenberger wrote: > > > I'm trying to add a X86 pattern to turn > > movl $-1, %eax > > into > > orl $-1, $eax > > Please make sure to measure the performance impact of doing this. You > are creating a false dependency on the last

...<regmask>, %RSP<imp-use>, %RDI<imp-use>, %RSP<imp-def>, %EAX<imp-def> ADJCALLSTACKUP64 0, 0, %RSP<imp-def,dead>, %EFLAGS<imp-def,dead>, %RSP<imp-use> %vreg4<def> = COPY %EAX; GR32:%vreg4 BURNSTACK %EFLAGS<imp-def,dead> %vreg5<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg5 %EAX<def> = COPY %vreg5; GR32:%vreg5 RETQ %EAX # End machine code for function main. Here is the dump after my custom inserter (with the stacktrace): # Machine code for function main: SSA BB#0: derived from LLVM BB %entry ADJCALLSTACKDOWN64 0, %RSP&...

...gt; | entry (0x8d4c6c0, LLVM BB @0x8d46970): | FNSTCW16m <fi#0>, 1, %NOREG, 0 int main() { | MOV8mi <fi#0>, 1, %NOREG, 1, 2 return 0; | FLDCW16m <fi#0>, 1, %NOREG, 0 } | %reg1024 = MOV32r0 | %EAX = MOV32rr %reg1024 | RET llc((anonymous namespace)::PrintStackTrace()+0x18)[0x88cfa30] llc((anonymous namespace)::SignalHandler(int)+0x107)[0x88cfcc1] /lib/tls/libc.so.6[0x239f48] llc(llvm::MachineFunctionPass::runOnFunction(llvm::Fu...

...t;imp-def,dead>, %EDI<imp-def,dead>, %EDX<imp-def,dead>, %ESI<imp-def,dead> 108 ADJCALLSTACKUP 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> 116 %reg1029<def,dead> = MOV32rr %EAX, %RAX<imp-use,kill> 124 %reg1030<def> = MOV32r0 %EFLAGS<imp-def,dead> 132 %EAX<def> = MOV32rr %reg1030<kill> 140 RET %EAX<imp-use,kill>, %AX<imp-use,kill> ********** REGISTER MAP ********** [reg1024 -> EAX] [reg1025 -> R10] [reg1026 -> AH] [reg1027 -> XMM10] [reg1028 -> R10] [reg1029 -> E...

...try (0x8d4c6c0, LLVM BB @0x8d46970): > | FNSTCW16m <fi#0>, 1, %NOREG, 0 > int main() { | MOV8mi <fi#0>, 1, %NOREG, 1, 2 > return 0; | FLDCW16m <fi#0>, 1, %NOREG, 0 > } | %reg1024 = MOV32r0 > | %EAX = MOV32rr %reg1024 > | RET > > llc((anonymous namespace)::PrintStackTrace()+0x18)[0x88cfa30] > llc((anonymous namespace)::SignalHandler(int)+0x107)[0x88cfcc1] > /lib/tls/libc.so.6[0x239f48] > llc(llvm::MachineFunc...

...TP64m %EBP, 1, %NOREG, -160 %EAX = MOV32rm %EBP, 1, %NOREG, -224 %EAX = ADD32ri8 %EAX, 24 %XMM0 = MOVSDrm %EBP, 1, %NOREG, -160 MOVSDmr %EBP, 1, %NOREG, -232, %XMM0 MOVSDmr %EAX, 1, %NOREG, 0, %XMM0 %EAX = CVTTSD2SIrm %ESI, 1, %NOREG, 0 %ECX = MOV32r0 TEST32rr %EAX, %EAX JNE mbb<bb.preheader.i271,0x8c55330> Successors according to CFG: 0x8c55330 0x8c573b0 The gdb disassembler gives me the following lines for that basic block __exp.exit: 0xf5f6f317: movl $0xa542b70,0xffffff20(%ebp) 0xf5f6f321: mov 0xffffff...

...;imp-def,dead>, > %EDX<imp-def,dead>, %ESI<imp-def,dead> > 108 ADJCALLSTACKUP 0, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, > %ESP<imp-use> > 116 %reg1029<def,dead> = MOV32rr %EAX, %RAX<imp-use,kill> > 124 %reg1030<def> = MOV32r0 %EFLAGS<imp-def,dead> > 132 %EAX<def> = MOV32rr %reg1030<kill> > 140 RET %EAX<imp-use,kill>, %AX<imp-use,kill> > > > ********** REGISTER MAP ********** > [reg1024 -> EAX] > [reg1025 -> R10] > [reg1026 -> AH] > [reg1027 ->...

Hi all, I'm trying to add a X86 pattern to turn movl $-1, %eax into orl $-1, $eax I can't find a way to express this in TableGen syntax though. def : Pat<(set GR32:$src, (i32 -1)), (OR32ri8 GR32:$src, -1)>; results in an assertion about 'Unknown Node'. Joerg

...g to CFG: BB#1 %RSP<def,tied1> = SUB64rr %RSP<tied0>, %RAX, %EFLAGS<imp-def>; flags: FrameSetup SEH_StackAlloc 40040; flags: FrameSetup SEH_EndPrologue; flags: FrameSetup %RCX<def> = LEA64r %RSP, 1, %noreg, 40, %noreg %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead> CALL64pcrel32 <ga:@dummy_use>, <regmask>, %RSP<imp-use>, %RCX<imp-use>, %EDX<imp-use,kill>, %RSP<imp-def> SEH_Epilogue %RSP<def,tied1> = ADD64ri32 %RSP<tied0>, 40040, %EFLAGS<imp-def,dead>...

...BB @0x8d46970): > > | FNSTCW16m <fi#0>, 1, %NOREG, 0 > > int main() { | MOV8mi <fi#0>, 1, %NOREG, 1, 2 > > return 0; | FLDCW16m <fi#0>, 1, %NOREG, 0 > > } | %reg1024 = MOV32r0 > > | %EAX = MOV32rr %reg1024 > > | RET > > > > llc((anonymous namespace)::PrintStackTrace()+0x18)[0x88cfa30] > > llc((anonymous namespace)::SignalHandler(int)+0x107)[0x88cfcc1] > > /lib/tls/libc.so.6[0x239f...

...xor idiom is recognized > >> by processors as old as Pentium 4 as having no dependencies. > > > > Any examples of how to create more than one instructions for a given > > pattern? There are some other cases I could use this for. > > def : Pat<(i32 -1), (DEC32r (MOV32r0))>; Hm. Right. This gives the me first set of size peep hole optmisations as attached. I didn't add the above rule for 64bit builds, since it is larger than the to-be-figured out OR32rmi8 / OR64rmi8. Joerg -------------- next part -------------- A non-text attachment was scrubbed... Name:...

On Tue, 18 Dec 2018 at 07:11, Gleb Popov via llvm-dev <llvm-dev at lists.llvm.org> wrote: > However, I haven't managed to get a "Constant<>" in the DAG when compiling for X86. I'm interested in how it is lowered. Can you please give me some guidance on this? How are you looking? When I run "llc -mtriple=x86_64-linux-gnu -debug-only=isel" on your IR I get

On Tue, Jul 28, 2015 at 6:34 PM, Reid Kleckner <rnk at google.com> wrote: > On Tue, Jul 28, 2015 at 2:25 AM, John Kåre Alsaker > <john.mailinglists at gmail.com> wrote: >> >> On Tue, Jul 28, 2015 at 12:44 AM, Reid Kleckner <rnk at google.com> wrote: >> > Yeah, the function attributes section of LangRef is a reasonable place >> > to >>

...;d> %mreg(100)<d> %mreg(101)<d> %mreg(102)<d> %mreg(17)<d> 36 ADJCALLSTACKUP 0, 0, %ESP<imp-def>, %ESP<imp-use> ADJCALLSTACKUP 0 0 %mreg(25)<d> %mreg(25) 40 %reg1026<dead> = MOV32rr %EAX<kill> MOV32rr %reg1026<d> %mreg(17) 44 %reg1027 = MOV32r0 MOV32r0 %reg1027<d> 48 %EAX = MOV32rr %reg1027<kill>, %RAX<imp-use,kill>, %RAX<imp-def> MOV32rr %mreg(17)<d> %reg1027 %mreg(74) %mreg(74)<d> 52 RET %EAX<imp-use,kill>, %RAX<imp-use,kill> RET %mreg(17) %mreg(74) (The CFE_* stuff is from our frontend)...

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined

...                                    . > > CMP32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>; > mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26 > > The relevant portion of the RDF graph that is constructed is shown below: > > BB#0: > > s3: MOV32r0 [d4<ECX>(,d50,u245):, d5<EFLAGS>!(,d7,):] > >                                                   . > >                                                   . > >                                                   . > > BB#1: > > s48: COPY [d49<CL>(...

...32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>; >>> mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26 >>> >>> The relevant portion of the RDF graph that is constructed is shown below: >>> >>> BB#0: >>> >>> s3: MOV32r0 [d4<ECX>(,d50,u245):, d5<EFLAGS>!(,d7,):] >>> >>> . >>> >>> . >>> >>> . >>...