llvm dev - Feb 2011 - [LLVMdev] Adding ARM/Thumb2 instructions with "S" suffux

Hello everyone,

I've added suffixed versions of ARM and Thumb2 instructions to tablegen.
That is, for example, "movs" or "orrs".
I implemented a rather simple codegen optimization which removes the
comparison in patterns like

orr r1, r2          --->     orrs r1, r2
cmp r1, 0

It works and have already shown nice acceleration (e.g., 3.3% in SQLite).

I have a few questions.

1)"neverHasSideEffects" in tablegen means CPSR is not implicitly
defined,
doesn't it?
2)What else can be optimized using that super "S" power?
3)Current optimization implementation works similar to peephole, but right
before ifcvt. Should I raise it up to somewhere else?
4)Please consider the following C code:

int a, b, c;
...
a = b * c;
if (a > 0) { ... }

One gets the corresponding ARM assembler

mul r(a), r(b), r(c)
cmp r(a), 1
blt LABEL

// r(x) in the register where x is

In the other cases ("if (a == 0)", "if (a < 0)") the
resultant comparison
is between r(a) and zero. So what is the hidden idea of comparing with 1
instead of producing

mul r(a), r(b), r(c)
cmp r(a), 0
ble LABEL

? Besides, where should I look for the code behind that?

Thanks,
  Vadim Markovtsev,
  ISP RAS.