llvm dev - Aug 2009 - [LLVMdev] LLVM performance tuning for target machines

I am currently looking at the Experimental MIPS backend and using it as a model.
One thing I am currently however not sure about is instruction scheduling. Does
LLVM have a pass which copes with instruction dependencies which will reorder
instructions to minimize latencies (and given a model of the CPU try to find a
good ordering for superscalar cpus? Is there an example of how this sort of
thing is done?

Thanks in advance.