similar to: [LLVMdev] LLVM performance tuning for target machines

Yes. But it is not really being used by most (any?) targets because post-RA scheduling is disabled by default. Also, the existing model is very limited in what types of micro-architectures can be described. I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages. See

On Sun, Aug 2, 2009 at 6:09 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code). Code generation actually was

I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code). --- On Sun, 8/2/09, Andrew Lenharth <andrewl at lenharth.org> wrote: > From: Andrew Lenharth <andrewl at

I posted an initial implementation that would generate code correctly, though I don't know that all optimization pass were safe still. see: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090511/077443.html As far as I know, there isn't enough demand right now for unions. They are mainly useful for target-independent front-ends. I don't have the time right now to push

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things. Thanks in advance, Carter.

Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen. --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote: > From: Carter Cheng <carter_cheng at yahoo.com> > Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc. > To: llvmdev at cs.uiuc.edu > Date:

Hi, I really dont know I came rather late to the discussion and some kind folks on this list gave me a few links. I didnt see much mention of any controversy. Are there issues still that need to be resolved? So far I am still quite the novice with LLVM internals but looking over the code it looks like one could hack in most of the required functionality up to the DAG building stage. I am not

Thanks for the help. I have a couple follow up questions- Where can I find the code which calculates the properties of inline asm nodes and examples of passes that make use of this information? Thanks again, Carter. On Mon, Nov 5, 2018 at 12:04 AM David Blaikie <dblaikie at gmail.com> wrote: > > > On Sun, Nov 4, 2018 at 1:56 AM Carter Cheng via llvm-dev < > llvm-dev at

I am curious- what is the current status of the MIPS support in LLVM? I have a mipsel device and was wondering if I could compile code for it with clang. Would I have to implement a backend setup myself? Is there also an option to compile w/ clang on an x86 for Mipsel? Thanks in advance.

Thanks both. I looked over the getelementptr and bitcast documentation but I am still a bit confused by one point. lets say i have something like this. union { long Int; double float; long* IntRef; } Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?

I am trying to create a boxed tagged datatype for a language where it is necessary to resolve the type at runtime. If I were writing an interpreter in C- it would most likely look something like this- struct { unsigned tag; union { long Int; double Float; .... } } Is there a standard way for constructing a type like this in LLVM? Thanks again.

This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? Thanks in advance.

On Oct 21, 2011, at 12:15 AM, James Molloy wrote: > Hi Andy, > > Could you describe how this would be done? In the current ARM itineraries > (say C-A9 for example), the superscalar issue stage is modelled as taking 1 > cycle. If it were to take 2 cycles instead, as far as I can tell the hazard > analyser would stall because both FU's would be acquired. > > I would

On Tue, Jun 30, 2009 at 12:16 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way? Not really; there's some discussion of that in the thread starting at

Eli Friedman wrote: > On Tue, Jun 30, 2009 at 12:16 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > >> Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way? >> > > Not really; there's some discussion of that in

On Mon, Jul 20, 2009 at 4:15 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? If you already have a cross-compiling environment set up, it shouldn't be too hard; for LLVM and llvm-gcc, you should be able to pass in --host=mytarget to configure, and if

On Mon, Jul 27, 2009 at 8:56 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > Is there also an option to compile w/ clang on an x86 for Mipsel? A normal build of clang includes limited cross-compile support by passing in the "-ccc-host-triple" option, although it's still a bit of a work-in-progress. Nobody has added support for any Mips targets, but it's really

On Sun, Aug 2, 2009 at 2:06 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

Hi, I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly more optimal code? (anyone have any references?) Thanks in advance.