llvm dev - Feb 2009 - [LLVMdev] Multiclass patterns

Is there a way to define a multi-class pattern in tablegen?

 

Thanks,

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

S1-609 One AMD Place

Sunnyvale, CA. 94085

P: 408-749-3966

 

 

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On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td,
et al.

-bw

Bill,
 Sorry if I wasn't clear enough. I wasn't referring to multiclass's
that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code. 
For example:
multiclass IntSubtract<SDNode node>
{
    def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
               (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
    def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
               (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
}

or something similar.
I just want to write the pattern once and then have it apply to multiple
register types, i.e. a generic pattern rule for many different register
classes.

Thanks,
Micah

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Bill Wendling
Sent: Monday, February 09, 2009 5:39 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Multiclass patterns

On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td,
et al.

-bw
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