Displaying 20 results from an estimated 24 matches for "gpri32".
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gpr32
2011 Sep 13
3
[LLVMdev] Setting priority in instruction selection
...amp; ~B), I have the following PatFrag:
/// Pattern 1: (lhs & bitpat) | (rhs & ~bitpat)
def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat),
(or
(and node:$lhs, node:$bitpat),
(and node:$rhs, (not node:$lhs)))>;
def BFI_i32 : ThreeInOneOut<IL_OP_BFI, (outs GPRI32:$dst),
(ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
!strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
[(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat))]>;
and also this instruction:
def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:...
2011 Sep 13
0
[LLVMdev] Setting priority in instruction selection
...n 1: (lhs & bitpat) | (rhs & ~bitpat)
>
> def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat),
>
> (or
>
> (and node:$lhs, node:$bitpat),
>
> (and node:$rhs, (not node:$lhs)))>;
>
> def BFI_i32 : ThreeInOneOut<IL_OP_BFI, (outs GPRI32:$dst),
>
> (ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
>
> !strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
>
> [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> GPRI32:$bitpat))]>;
>
> and also this instruction:
>
>
>...
2008 Oct 30
1
[LLVMdev] Using patterns inside patterns
I do not have access to a subtraction routine, as it is considered add
with negation on the second parameter, so I have this pattern:
// integer subtraction
// a - b ==> a + (-b)
def ISUB : Pat<(sub GPRI32:$src0, GPRI32:$src1),
(IADD GPRI32:$src0, (INEGATE GPRI32:$src1))>;
I am attemping to do 64 bit integer shifts and using the following
pattern:
def LSHL : Pat<(shl GPRI64:$src0, GPRI32:$src1),
(LCREATE (ISHL (LLO GPRI64:$src0), GPRI32:$src1),
(IOR (ISH...
2011 Sep 13
1
[LLVMdev] Setting priority in instruction selection
...>
> > def bfi_pat1 : PatFrag<(ops node:$lhs, node:$rhs, node:$bitpat),
> >
> > (or
> >
> > (and node:$lhs, node:$bitpat),
> >
> > (and node:$rhs, (not node:$lhs)))>;
> >
> > def BFI_i32 : ThreeInOneOut<IL_OP_BFI, (outs GPRI32:$dst),
> >
> > (ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
> >
> > !strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
> >
> > [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> > GPRI32:$bitpat))]>;
> >
> &...
2008 Oct 30
0
[LLVMdev] Using patterns inside patterns
I am not sure what you are looking to do. Please provide a mark up
example.
Evan
On Oct 28, 2008, at 11:00 AM, Villmow, Micah wrote:
> Is there currently a way to use a pattern inside of another pattern?
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P:
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...eg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern...
2008 Oct 28
4
[LLVMdev] Using patterns inside patterns
Is there currently a way to use a pattern inside of another pattern?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...eg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
...define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
(ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
}
or something similar.
I just want to write the pattern once and then have it apply to multiple
register types, i.e. a generic pattern rule for many different register
classes.
Thanks,
Micah
-----Origina...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...c0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> class ILFormat<dag outs, dag ins, string...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...c0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> class ILFormat<dag outs, dag ins, string...
2009 Feb 10
0
[LLVMdev] Multiclass patterns
...using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
> (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
> def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
> (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
> }
>
> or something similar.
> I just want to write the pattern once and then have it apply to multiple
> register types, i.e. a generic pattern rule for many different register
> clas...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Is there a way to define a multi-class pattern in tablegen?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
S1-609 One AMD Place
Sunnyvale, CA. 94085
P: 408-749-3966
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2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al.
-bw
2012 Aug 15
0
[LLVMdev] More Back-End Porting Troubles
...normal nodes"
> when lowering a specific instruction within the TargetLowering?
[Villmow, Micah] Have you tried using a tablegen pattern here? I find it is easier for simple conversions like this than using C++ code.
For example our backend does this with:
def uitoli64rr:Pat < (i64 (zext GPRI32:$src)), (LCREATEi64rr GPRI32:$src, (LOADCONSTi32 0)) >;
Where LCREATE is a machine instruction that does similar to ISD::BUILD_PAIR from two i32's and outputs a i64.
>
> Any hints are highly welcome!
>
> Ciao, Fabian
> _______________________________________________
> LL...
2008 Oct 24
2
[LLVMdev] SetCC tablegen pattern
...src0, $src1", [(set GPRF32:$dst, (seteq
GPRF32:$src0, GPRF32:$src1))]>;
And it is failing stating that the result must be an integer. Is there a
way around this other than modifying TargetSelectionDAG.td? Also, why is
it assumed that all comparison results are always integers?
If I put GPRI32 as my destination register, it complains about register
classes not matching......
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
-------------- nex...
2012 Aug 16
2
[LLVMdev] More Back-End Porting Troubles
...eneral problem (there are more back-ends
having '[]'-patterns).
> [Villmow, Micah] Have you tried using a tablegen pattern here? I find it is easier for simple conversions like this than using C++ code.
> For example our backend does this with:
> def uitoli64rr:Pat < (i64 (zext GPRI32:$src)), (LCREATEi64rr GPRI32:$src, (LOADCONSTi32 0)) >;
> Where LCREATE is a machine instruction that does similar to ISD::BUILD_PAIR from two i32's and outputs a i64.
>
I already tried to use a pattern, but for some reason I messed it up.
Giving it another try now, I finally succeede...
2008 Oct 25
0
[LLVMdev] SetCC tablegen pattern
...(seteq
> GPRF32:$src0, GPRF32:$src1))]>;
>
> And it is failing stating that the result must be an integer. Is
> there a way around this other than modifying TargetSelectionDAG.td?
> Also, why is it assumed that all comparison results are always
> integers?
> If I put GPRI32 as my destination register, it complains about
> register classes not matching……
>
>
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
&g...
2012 Aug 15
5
[LLVMdev] More Back-End Porting Troubles
Hi LLVM-Folks,
as mentioned in an earlier post
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051677.html) I
am currently working on a Back-End for the TriCore processor.
Currently, I am struggling as LLVM could not select zext and load, for
instance, so some of the testcases in test/CodeGen/Generic are not
successfully compiled by my back-end.
Furthermore, I am completely puzzled by the
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the