Displaying 9 results from an estimated 9 matches for "gpri8".
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2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill,
Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
(ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
}
or something similar.
I just want to write the pattern once and then have it apply...
2009 Feb 10
0
[LLVMdev] Multiclass patterns
...l,
> Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
> define other classes, but with using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
> (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
> def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
> (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
> }
>
> or something similar.
> I just want to write the patte...
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I wan...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
!strconcat(op.Text, " $dst, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I wan...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...uts dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
> !strconcat(op.Text, " $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCIn...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Is there a way to define a multi-class pattern in tablegen?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
S1-609 One AMD Place
Sunnyvale, CA. 94085
P: 408-749-3966
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2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al.
-bw
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...uts dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
> !strconcat(op.Text, " $dst, $src0, $src1"),
> [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCIn...
2011 Oct 20
2
[LLVMdev] Emulate i64 add with 3 instructions
Hello!
Is there a way to tell LLVM how to emulate an instruction with multiple
others? Specifically, in our processor, there is no instruction for
adding two i64s; it has to be done like this
dst_high32:dst_low32 = src1_low32 + src2_low32 (unsigned add; dst_high
might contain the overflow bit)
dst_high32 = dst_high32 + src1_high32
dst_high32 = dst_high32 + src2_high32
I tried it with