Hi all, How do I generate the movq2dq SSE2 instruction using the IRBuilder? There is no zext from 64-bit to 128-bit (corresponding to MMX to XMM register transfer) as far as I can tell. So I've tried inserting an i64 into a v2i64, which generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instructions. I couldn't find ways to generate these instructions. I believe they should also be supported as intrinsics, so if anyone could check whether or not that works, and if so, how I could do it using the IRBuilder, that would be very much appreciated. Cheers, Nicolas Capens -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080731/04e5985f/attachment.html>
In the same breath I'd also like to kindly ask if someone could have a look at the reverse operations, namely trunk from 128 to 64 bit using movdq2q, and 128 to 32 and 64 to 32 using movd. This also seems related to Bug 2585. Thanks again. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Nicolas Capens Sent: Thursday, 31 July, 2008 16:03 To: 'LLVM Developers Mailing List' Subject: [LLVMdev] Generating movq2dq using IRBuilder Hi all, How do I generate the movq2dq SSE2 instruction using the IRBuilder? There is no zext from 64-bit to 128-bit (corresponding to MMX to XMM register transfer) as far as I can tell. So I've tried inserting an i64 into a v2i64, which generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instructions. I couldn't find ways to generate these instructions. I believe they should also be supported as intrinsics, so if anyone could check whether or not that works, and if so, how I could do it using the IRBuilder, that would be very much appreciated. Cheers, Nicolas Capens -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080731/f34ea85f/attachment.html>
On Jul 31, 2008, at 7:22 AM, Nicolas Capens wrote:> In the same breath I’d also like to kindly ask if someone could have > a look at the reverse operations, namely trunk from 128 to 64 bit > using movdq2q, and 128 to 32 and 64 to 32 using movd. This also > seems related to Bug 2585. Thanks again.The operations you're describing can be represented as insertelement and extractelement in LLVM IR. I don't know of anyone actively working on MMX tuning for LLVM, so if you'd like to see it improve, consider yourself encouraged to get involved directly :-). Dan