search for: mmx_movq2dqrr

...ch generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instructions. I couldn't find ways to generate these instructions. I believe they should also be supported as intrinsics, so if...

...e been able to fix the first two definitions by using MRMSrcReg (and set > hasNoSideEffects). I’m not sure about the third definition though, is this > for 3DNow! And should it use MRMSrcReg as well? Also fixed in r75142. Note that MMX_MOVQ2FR64rr is actually exactly the same instruction as MMX_MOVQ2DQrr; they're separated because it's a bit more straightforward to write that way (FR64 and VR128 are both XMM registers, but TableGen isn't aware of the precise relationship). -Eli

Hi all, I believe I've found a bug in the encoding of the movd instruction on x64. Here's some IR code to reproduce it: external global i8*, align 1 ; <i8**>:0 [#uses=1] external global i8*, align 16 ; <i8**>:1 [#uses=1] declare void @abort() define internal void @2() { %1 = load i8** @0, align 1 ; <i8*> [#uses=1] %2 =

...ch generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instructions. I couldn't find ways to generate these instructions. I believe they should also be supported as intrinsics, so if...