search for: x86gendagisel

...e it is a non-suffixed constant). Regarding the email I *just* send about the INT64_C macros and so forth, the 1 should actually be INT64_C(1) and that should fix it. Also, getting another set of warning, but the file looks fine, so do not know... R:\SDKs\llvm\trunk_VC8_building\lib\Target\X86\X86GenDAGISel.inc(54113) : warning C4065: switch statement contains 'default' but no 'case' labels R:\SDKs\llvm\trunk_VC8_building\lib\Target\X86\X86GenDAGISel.inc(54121) : warning C4065: switch statement contains 'default' but no 'case' labels R:\SDKs\llvm\trunk_VC8_building\lib\...

...e it is a non-suffixed constant). Regarding the email I *just* send about the INT64_C macros and so forth, the 1 should actually be INT64_C(1) and that should fix it. Also, getting another set of warning, but the file looks fine, so do not know... R:\SDKs\llvm\trunk_VC8_building\lib\Target\X86\X86GenDAGISel.inc(54113) : warning C4065: switch statement contains 'default' but no 'case' labels R:\SDKs\llvm\trunk_VC8_building\lib\Target\X86\X86GenDAGISel.inc(54121) : warning C4065: switch statement contains 'default' but no 'case' labels R:\SDKs\llvm\trunk_VC8_building\lib\...

...cursive function (??), it seems an inherent limitation in how big llvm functions can be. Simon. gdb backtrace: #0 0x40b126a3 in (anonymous namespace)::X86DAGToDAGISel::Select_store(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:19768 #1 0x40b01b44 in (anonymous namespace)::X86DAGToDAGISel::SelectCode(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:27833 #2 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand...

...cursive function (??), it seems an inherent limitation in how big llvm functions can be. Simon. gdb backtrace: #0 0x40b126a3 in (anonymous namespace)::X86DAGToDAGISel::Select_store(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:19768 #1 0x40b01b44 in (anonymous namespace)::X86DAGToDAGISel::SelectCode(llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at X86GenDAGISel.inc:27833 #2 0x40ada64f in (anonymous namespace)::X86DAGToDAGISel::Select(llvm::SDOperand...

I've got the following problem in the X86 selector generated by TableGen: llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here This seems to happen because of a pattern I added for VEXTRACTF128 which uses extract_subreg: [(set DSTREGCLASS:$dst, (DSTTYPE (extract_subreg (vector_shuffle...

...n > in how big llvm functions can be. > > Simon. > > gdb backtrace: > #0 0x40b126a3 in (anonymous > namespace)::X86DAGToDAGISel::Select_store(llvm::SDOperand&, > llvm::SDOperand) (this=0x822d660, > Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at > X86GenDAGISel.inc:19768 > #1 0x40b01b44 in (anonymous namespace)::X86DAGToDAGISel::SelectCode > (llvm::SDOperand&, llvm::SDOperand) (this=0x822d660, > Result=@0xbf800a10, N={Val = 0x8254338, ResNo = 0}) at > X86GenDAGISel.inc:27833 > #2 0x40ada64f in (anonymous namespace)::X86DAGToDAG...

...sers/peckw/Projects/llvm/llvm-pristine/lib/Target/X86 -I /Users/peckw/Projects/llvm/llvm-pristine/include -I /Users/peckw/Projects/llvm/llvm-pristine/include -I /Users/peckw/Projects/llvm/llvm-pristine/lib/Target -gen-dag-isel -o /Users/peckw/Projects/llvm/build/pristine/lib/Target/X86/Debug+Checks/X86GenDAGISel.inc.tmp /Users/peckw/Projects/llvm/llvm-pristine/lib/Target/X86/X86.td make[3]: *** [/Users/peckw/Projects/llvm/build/pristine/lib/Target/X86/Debug+Checks/X86GenDAGISel.inc.tmp] Abort trap I get this build error on every single backend when building the DAG Instruction selector using tblgen. This...

On Thursday 03 December 2009 13:39, David Greene wrote: > I've got the following problem in the X86 selector generated by > TableGen: > > llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value > llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here > > This seems to happen because of a pattern I added for VEXTRACTF128 which > uses extract_subreg: > > [(set DSTREGCLASS:$dst, > (DSTTYPE (extract_subreg &gt...

...simplified.bc. I run llc on this file with all LLVM register allocators and it gives the same result (under gdb): Program received signal SIGSEGV, Segmentation fault. 0x00634572 in (anonymous namespace)::X86DAGToDAGISel::DeleteNode ( this=0x4c3b710, N=0x4c3e5c0) at /llvm/obj/lib/Target/X86/X86GenDAGISel.inc:77 77 SDNode *Operand = I->Val; SEGFAULT seems to come before register allocation pass is being run. Thanks. -- Three things are certain: Death, taxes, and lost data. Guess which has occurred. -------------- next part -------------- An HTML attachment was scrubbed... URL: <ht...

...projects/compiler-rt/lib/tsan/rtl/tsan_interceptors.cc:2367: /home/sbruno/clang/llvm/projects/compiler-rt/lib/tsan/../sanitizer_common/sanitizer_common_interceptors.inc:41:10: fatal error: 'stdarg.h' file not found #include <stdarg.h> ^ 1 error generated. [1950/2811] Building X86GenDAGISel.inc... ninja: build stopped: subcommand failed.

...t (corresponding to MMX to XMM register transfer) as far as I can tell. So I've tried inserting an i64 into a v2i64, which generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instruc...

...> > Ping? Just want to make sure this didn't get missed somehow. I'm > surprised to see no discussion. I've now looked at your latest patch. In summary, it does expose a subtle problem. I haven't seen anything that here would lead to observable misbehavior yet though. X86GenDAGISel.inc has code like this: SDValue N1 = N->getOperand(1); ... SDNode *ResNode = CurDAG->SelectNodeTo(N, ...); ... ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 2)); If N was the only user of N1, and N1 isn't in the new operand list, then the SelectNodeTo call will m...

...the X86 backend that appears when I build with VC8. I've managed to fix it by duplicating the std::vector in question before iterating through it, but I'm too new to the code to be able to say whether it's the "right" fix. The offending bit of generated code is this area from X86GenDAGISel.inc, line 84+: // ReplaceHandles - Replace all the handles with the real target // specific nodes. void ReplaceHandles() { for (std::map<SDOperand, SDOperand>::iterator I = ReplaceMap.begin(), E = ReplaceMap.end(); I != E; ++I) { SDOperand From = I->first; SDOpera...

On Friday 26 February 2010 10:34:41 David Greene wrote: > On Friday 26 February 2010 09:55:32 David Greene wrote: > > In the continuing quest to try to track down problems we're seeing in > > SelectionDAG, I added the following assert > > toSelectionDAG::ReplaceAllUsesOfValuesWith: > > Here's a patch to add more of these deleted node asserts. They fire > tons

...ebug\X86CommonTableGen\X86Commo.1917F16D.tlog\unsuccessfulbuild" wird erstellt, da "AlwaysCreate" angegeben wurde. CustomBuild:   Building X86GenAsmMatcher.inc...   Building X86GenAsmWriter.inc...   Building X86GenAsmWriter1.inc...   Building X86GenCallingConv.inc...   Building X86GenDAGISel.inc...   Building X86GenDisassemblerTables.inc...   Building X86GenEVEX2VEXTables.inc...   Building X86GenFastISel.inc...   Building X86GenGlobalISel.inc...   ... which costs me much time (>30min) on my slow system - and i don't understand why "AlwaysCreate" is used here - i...

...JIT calls into. I think its expected the user would call it or pass a specific CPU string to the MCPU for the EngineBuilder. But getHostCPUName in LLVM 3.5 doesn't recognize Kabylake or Skylake. The Cannot select: means that an intrinsic was used but no pattern could be found in lib/Target/X86/X86GenDAGISel.inc that applies to the enabled feature set. We have separate patterns for that intrinsic for at least SSE4.1 and AVX1 in 3.5. So that implies that the EngineBuilder thinks your CPU doesn't support SSE4.1 or AVX1 either. But I'm not sure why you would be getting different behavior on Kabyla...

...ed things this way: legalize | V manual lowering (X86ISelLowering) | V manual isel (X86ISelDAGToDAG) | V table-driven isel (.td files/X86GenDAGISel) | V manual isel (some to-be-design piece) The idea is that we keep the existing manual pieces where they are to clean things up for TableGen-based isel and/or handle special cases. Maybe we consider getting rid of some in the future but that's a...

On Sun, 3 Sep 2006, Tanya M. Lattner wrote: >> BTW, how can I run all tests only on LLC to reduce the amount of time to >> wait until tests are finished, if it's possible? > > In my previous reply to your question, I suggested you look at > TEST.llc.Makefile and TEST.llc.report in the test directory. Modifying > those makefile/report files to use your register allocator

...legalize > | > V > manual lowering (X86ISelLowering) > | > V > manual isel (X86ISelDAGToDAG) > | > V > table-driven isel (.td files/X86GenDAGISel) > | > V > manual isel (some to-be-design piece) > > The idea is that we keep the existing manual pieces where they are to > clean things up for TableGen-based isel and/or handle special cases. > Maybe we consider getting rid of som...

...t (corresponding to MMX to XMM register transfer) as far as I can tell. So I've tried inserting an i64 into a v2i64, which generates valid code but rather a number of stores and loads on the stack instead of a single movq2dq. Looking though the code, I found a pattern for the instruction in X86GenDAGISEL.inc, but it describes a i64 to v2i64 bitcast (which isn't allowed by IRBuilder). Also, it is described as MMX_MOVQ2DQrr and only checks for MMX support, while it's really an SSE2 instruction. Actually zext from 32 to 64 and 32 to 128 bit would also be useful, using movd and movq instruc...