arm: implement ARMv7 tlb ops.
xen/arch/arm/xen/Makefile | 1 +
xen/arch/arm/xen/cache-v7.S | 17 +++++------------
xen/arch/arm/xen/domain_build.c | 6 +++---
xen/arch/arm/xen/tlb-v7.S | 51
+++++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 60 insertions(+), 15 deletions(-)
Signed-off-by: Jaemin Ryu <jm77.ryu@samsung.com>
diff -r c6a412adfae7 xen/arch/arm/xen/Makefile
--- a/xen/arch/arm/xen/Makefile Sun Feb 12 12:05:36 2012 +0900
+++ b/xen/arch/arm/xen/Makefile Sun Feb 12 12:24:09 2012 +0900
@@ -23,3 +23,4 @@ obj-y += perfmon.o
obj-y += pci.o
obj-y += armv7.o
obj-y += cache-v7.o
+obj-y += tlb-v7.o
diff -r c6a412adfae7 xen/arch/arm/xen/cache-v7.S
--- a/xen/arch/arm/xen/cache-v7.S Sun Feb 12 12:05:36 2012 +0900
+++ b/xen/arch/arm/xen/cache-v7.S Sun Feb 12 12:24:09 2012 +0900
@@ -1,7 +1,6 @@
-#include <xen/linkage.h>
+#include <xen/config.h>
+#include <asm/asm-macros.h>
#include <asm/page.h>
-#include <asm/cpu-ops.h>
-#include <asm/system.h>
#include <asm/asm-offsets.h>
.macro v7_way_op, op
@@ -49,7 +48,7 @@ 50:
.endm
.text
-PRIVATE(v7_flush_cache_all)
+ENTRY(cpu_flush_cache_all)
stmfd sp!, {r4-r5, r7, r9-r11, lr}
v7_way_op c14
@@ -59,9 +58,7 @@ PRIVATE(v7_flush_cache_all)
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_all, v7_flush_cache_all)
-
-PRIVATE(v7_flush_cache_range)
+ENTRY(cpu_flush_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
mov r3, #16 @ size offset
@@ -74,9 +71,7 @@ 1:
dsb
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_range, v7_flush_cache_range)
-
-PRIVATE(v7_clean_cache_range)
+ENTRY(cpu_clean_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
mov r3, #16 @ size offset
@@ -90,5 +85,3 @@ 1:
dsb
mov pc, lr
-DECLARE_CPU_OP(cpu_clean_cache_range, v7_clean_cache_range)
-
diff -r c6a412adfae7 xen/arch/arm/xen/domain_build.c
--- a/xen/arch/arm/xen/domain_build.c Sun Feb 12 12:05:36 2012 +0900
+++ b/xen/arch/arm/xen/domain_build.c Sun Feb 12 12:24:09 2012 +0900
@@ -176,7 +176,7 @@ int domain_construct(struct domain *d,
} while(gpt++, pmap < pend);
/* Activate guest address space to relocate guest image */
- mmu_switch_ttb(gpt & ~(0x4000 - 1));
+ set_ttbr((unsigned long)(gpt) & ~(0x4000 - 1));
elf.dest = (void *)ventry;
elf_load_binary(&elf);
@@ -192,7 +192,7 @@ int domain_construct(struct domain *d,
si->mfn_list = 0;
si->first_p2m_pfn = pstart >> PAGE_SHIFT;
si->flags = 0;
- si->min_mfn = pstart >> PAGE_SHIFT;
+ //si->min_mfn = pstart >> PAGE_SHIFT;
if (d->domain_id == 0) {
si->flags = SIF_PRIVILEGED | SIF_INITDOMAIN;
@@ -202,7 +202,7 @@ int domain_construct(struct domain *d,
VCPU_REG(v, ttbr0) = (unsigned long)gpt;
- mmu_switch_ttb(VCPU_REG(idle_vcpu[0], ttbr0));
+ set_ttbr(VCPU_REG(idle_vcpu[0], ttbr0));
vcpu_context_init(v, 0, ventry, si);
diff -r c6a412adfae7 xen/arch/arm/xen/tlb-v7.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/xen/arch/arm/xen/tlb-v7.S Sun Feb 12 12:24:09 2012 +0900
@@ -0,0 +1,51 @@
+#include <xen/config.h>
+#include <asm/asm-macros.h>
+#include <asm/page.h>
+
+#define PAGE_SZ 4096 /* PAGE_SIZE @ */
+
+ENTRY(cpu_flush_tlb_all)
+ dsb
+ mov ip, #0
+#ifndef SMP
+ mcr p15, 0, ip, c8, c6, 0 @ invalidate Entire I TLB
+ mcr p15, 0, ip, c8, c5, 0 @ invalidate Entire D TLB
+#else
+ mcr p15, 0, ip, c8, c3, 0
+#endif
+ mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB (shareable)
+ dsb
+ isb
+ mov pc, lr
+
+ENTRY(cpu_flush_tlb_entry)
+ dsb
+#ifndef SMP
+ mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
+ mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
+#else
+ mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
+#endif
+ mov ip, #0
+ mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB (shareable)
+ dsb
+ mov pc, lr
+
+ENTRY(cpu_flush_tlb_range)
+ dsb
+1:
+#ifndef SMP
+ mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
+ mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
+#else
+ mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
+#endif
+ add r0, r0, #PAGE_SZ
+ cmp r0, r1
+ blo 1b
+ mov ip, #0
+ mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB (shareable)
+ dsb
+ isb
+ mov pc, lr
+
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