Displaying 1 result from an estimated 1 matches for "csidr".
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cidr
2012 Feb 13
0
[PATCH 10/14] arm: implement ARMv7 tlb ops.
...{r4-r5, r7, r9-r11, lr}
v7_way_op c14
@@ -59,9 +58,7 @@ PRIVATE(v7_flush_cache_all)
ldmfd sp!, {r4-r5, r7, r9-r11, lr}
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_all, v7_flush_cache_all)
-
-PRIVATE(v7_flush_cache_range)
+ENTRY(cpu_flush_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
mov r3, #16 @ size offset
@@ -74,9 +71,7 @@ 1:
dsb
mov pc, lr
-DECLARE_CPU_OP(cpu_flush_cache_range, v7_flush_cache_range)
-
-PRIVATE(v7_clean_cache_range)
+ENTRY(cpu_clean_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and...