There''s been a lot of debate as to whether the Invariant TSC flag in recent Intel and AMD processors should be "trusted" by Xen, especially on larger multi-socket or multi-enclosure systems. I recently learned an interesting fact that reinforces this trust: On Intel QPI and AMD HT systems, the clock signal that is used to drive the Invariant TSC is the same one that is used for the system-wide cache-coherency protocol! IOW on any ccNUMA system where the TSC invariant bit is set on any processor, TSC invariance applies to all processors, or the system is broken. This means that if: 1) The Invariant TSC bit is set; and 2) The BIOS has sync''ed the TSC''s (which can be tested once at boot time by Xen using the newly added check_tsc_warp() routine); and 3) System software (Xen) never writes to any TSC on any processor (which is true in Xen when the Invariant TSC bit is set after a recent patch); then the TSC is "reliable" across all processors and will remain reliable and any difference (e.g. due to signal propagation delays) will be unobservable by software.... that is "time" will never go backwards. While my personal main concern involves TSC in userland, TSC reliability has other (minor) implications inside Xen itself: 1) Performance: Xen''s 1 Hz clock synchronization mechanism is (I think) entirely unneeded. 2) Power: An idle system can (I think) now be truly tickless. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel