Xen devel - May 2008 - [PATCH] Fix lapic timer stop issue in deep C state

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this
patch add the logic that use platform timer (HPET) to reenable local
APIC timer at C state entry/exit.

Signed-off-by: Wei Gang <gang.wei@intel.com>
Signed-off-by: Yu Ke <ke.yu@intel.com>


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Fix 32pae build.

Jimmy

On Tuesday, May 20, 2008 11:22 PM, Wei, Gang wrote:
> Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this
> patch add the logic that use platform timer (HPET) to reenable local
> APIC timer at C state entry/exit.
> 
> Signed-off-by: Wei Gang <gang.wei@intel.com>
> Signed-off-by: Yu Ke <ke.yu@intel.com>

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Applied, after a lot of restructuring.

Also, would it be cleaner to set up the HPET to do direct FSB writes to a
local APIC, rather than hijacking PIT ch0? There are some corner cases where
we leave PIT ch0 enabled after boot. Do most HPET implementations support
direct FSB interrupt delivery?

 -- Keir

On 20/5/08 16:22, "Wei, Gang" <gang.wei@intel.com> wrote:
> Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this
> patch add the logic that use platform timer (HPET) to reenable local
> APIC timer at C state entry/exit.
> 
> Signed-off-by: Wei Gang <gang.wei@intel.com>
> Signed-off-by: Yu Ke <ke.yu@intel.com>


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Using HPET direct FSB interrupt delivery is the right thing to do in
next step. I am not sure whether most existing HPET implementation
support it, but most future implementations should definitely support
it.

Jimmy

On Wednesday, May 21, 2008 5:55 PM, Keir Fraser wrote:
> Applied, after a lot of restructuring.
> 
> Also, would it be cleaner to set up the HPET to do direct FSB writes
to a
> local APIC, rather than hijacking PIT ch0? There are some corner cases
> where we leave PIT ch0 enabled after boot. Do most HPET
implementations
> support direct FSB interrupt delivery?
> 
>  -- Keir
> 
> On 20/5/08 16:22, "Wei, Gang" <gang.wei@intel.com> wrote:
> 
>> Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this
>> patch add the logic that use platform timer (HPET) to reenable local
>> APIC timer at C state entry/exit.
>> 
>> Signed-off-by: Wei Gang <gang.wei@intel.com>
>> Signed-off-by: Yu Ke <ke.yu@intel.com>
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Thanks for the restructuring, Yes, FSB delivery mode (MSI) support is in
our next plan.

HPET in ICH7/8/9 has only IOAPIC mode. ICH10 will add  FSB mode. 

Best Regards
Ke

Keir Fraser wrote:
> Applied, after a lot of restructuring.
> 
> Also, would it be cleaner to set up the HPET to do direct FSB writes
> to a local APIC, rather than hijacking PIT ch0? There are some corner
> cases where we leave PIT ch0 enabled after boot. Do most HPET
> implementations support direct FSB interrupt delivery?
> 
>  -- Keir
> 
> On 20/5/08 16:22, "Wei, Gang" <gang.wei@intel.com> wrote:
> 
>> Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this
>> patch add the logic that use platform timer (HPET) to reenable local
>> APIC timer at C state entry/exit.
>> 
>> Signed-off-by: Wei Gang <gang.wei@intel.com>
>> Signed-off-by: Yu Ke <ke.yu@intel.com>

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