similar to: [PATCH] x86-64: refine access permission check for wrmsr to MSR_FAM10H_MMIO_CONF_BASE

Make sure the upper 32 bits of RAX are disregarded during MSR write emulation. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/traps.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/traps.c 2007-08-08 11:37:08.000000000 +0200 +++ 2007-08-08/xen/arch/x86/traps.c 2007-08-08 11:40:02.000000000 +0200 @@

In this patch, we change read_segment_register to take vcpu and regs parameters for PVH (in upcoming patches). No functionality change. also, make emulate_privileged_op() public for later. Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com> diff -r 93d95f6dd693 -r 0339f85f6068 xen/arch/x86/domain.c --- a/xen/arch/x86/domain.c Fri Jan 11 16:22:57 2013 -0800 +++ b/xen/arch/x86/domain.c

I recently realized that the original way of dealing with the DebugCtl MSR on VMX failed to make use of the dedicated guest VMCS field. This is being fixed with this patch. What is puzzling me to a certain degree is that while there is a guest VMCS field for this MSR, there''s no equivalent host load field, but there''s also no indication that the MSR would be cleared during a

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

(Applies cleanly only on top of the previously sent SVM/LBR patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/svm/svm.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:40:11.000000000 +0200 +++ 2007-08-08/xen/arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200

"Jan Beulich" <JBeulich at suse.com> writes: #Okay, this at least clarifies there is a (relatively big) RMRR. There is #a change to the handling of these among the ones that'll become #4.3.3 - mind giving #http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=6c63041428cc348bcb2887afabd606bc4bd5523f #a try on top of your 4.3.2 (or trying the tip of the stable-4.3 branch)? #

>>> On 22.05.14 at 19:19, <mike at estone.ca> wrote: > "Jan Beulich" <JBeulich at suse.com> writes: > #Okay, this at least clarifies there is a (relatively big) RMRR. There is > #a change to the handling of these among the ones that'll become > #4.3.3 - mind giving > #http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=6c63041428cc348bcb2 >

x86:x2apic: Disable x2apic on x86-32 permanently x2apic initialization on x86_32 uses vcpu pointer before it is initialized. As x2apic is unlikely to be used on x86_32, this patch disables x2apic permanently on x86_32. It also asserts the sanity of vcpu pointer before dereference to prevent further misuse. Signed-off-by: Fengzhe Zhang <fengzhe.zhang@intel.com> diff -r 02c0af2bf280

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> ---

Xen is compiled with no -O gcc option, meaning no optimization, and the compiler does the safest thing imaginable. This means that if a function, say vmx_world_save(), calls the same inline a bazillion times, the stack will have one block of local variables for each invocation of that function! Xen really should not be doing this. We could either uninline some of these functions, or try gcc -O2

From: Yang Zhang <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git

From eb20603913ff7350cd25b39d1eb37b8fddd16053 Mon Sep 17 00:00:00 2001 From: Zhang Xiantao <xiantao.zhang@intel.com> Date: Sat, 25 Aug 2012 04:11:08 +0800 Subject: [PATCH 2/2] Nested: VM_ENTRY_IA32E_MODE shouldn''t be in default1 class for IA32_VM_ENTRY_CTLS_MSR. If set to 1, L2 guest''s paging mode maybe mis-judged and mis-set. Signed-off-by: Zhang Xiantao

Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen Signed-off-by: Wei Gang <gang.wei@intel.com> diff -r bd683e0397b4 xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Tue Feb 17 22:29:38 2009 +0800 +++ b/xen/arch/x86/traps.c Wed Feb 25 11:23:01 2009 +0800 @@ -2187,10 +2187,17 @@ static int emulate_privileged_op(struct case MSR_IA32_MPERF: case MSR_IA32_APERF:

TPR shadow/threshold feature is important to speedup the boot time for Windows guest. Besides, it is a must feature for certain VMM. We map virtual APIC page address and TPR threshold from L1 VMCS, and synch it into shadow VMCS in virtual vmentry. If TPR_BELOW_THRESHOLD VM exit is triggered by L2 guest, we inject it into L1 VMM for handling. Besides, this commit fixes an issue for apic access

Utilize some of the additions in the prior patches to clean up other code: - keep track of REP prefixes in only one variable - use REX_W in a few more places (instead of a literal number) Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -304,6 +304,10 @@ union vex { ptr[1] = rex |

Add the new MEM_EVENT_REASON_MSR event type. Works similarly to the other register events, except event.gla always contains the MSR address (in addition to event.gfn, which holds the value). MEM_EVENT_REASON_MSR does not honour the HVMPME_onchangeonly bit, as doing so would complicate the hvm_msr_write_intercept() switch-based handling of writes for different MSR addresses, with little added

Hi all, I have installed a CentOS-8 server to accomplish some tests using kvm guests ? All these guests are centos8 also. When these guests starts, I always see errors like: [ 589.687915] kvm [2133]: vcpu0, guest rIP: 0xffffffff81a5bc98 disabled perfctr wrmsr: 0xc2 data 0xffff [ 596.210773] kvm [2201]: vcpu0, guest rIP: 0xffffffffb885bc98 disabled perfctr wrmsr: 0xc2 data 0xffff Is this a

Can you please check the vcpu status? I suspect one of the vcpu is blocked by halt instruction. Thanks Yunhong Jiang >-----Original Message----- >From: xen-devel-bounces@lists.xensource.com >[mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Tim Deegan >Sent: 2006年10月5日 23:55 >To: Li, Xin B >Cc: xen-devel@lists.xensource.com >Subject: Re: [Xen-devel] [PATCH] add

Add the new MEM_EVENT_REASON_MSR event type. Works similarly to the other register events, except event.gla always contains the MSR type (in addition to event.gfn, which holds the value). Signed-off-by: Razvan Cojocaru <rzvncj@gmail.com> Acked-by: Tim Deegan <tim@xen.org> diff -r b04de677de31 -r e33d3d37dfbf xen/arch/x86/hvm/hvm.c --- a/xen/arch/x86/hvm/hvm.c Tue Dec 18 18:16:52 2012

Svm patch to add 32bit msr support (combined both 32bit with 64bit functions) and enable vlapic for 64bit. Applies cleanly to 9023. Please apply. Signed-off-by: Tom Woller <thomas.woller@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel