Xen devel - Jan 2013 - [PATCH V4] mem_event: Add support for MEM_EVENT_REASON_MSR

Add the new MEM_EVENT_REASON_MSR event type. Works similarly
to the other register events, except event.gla always contains
the MSR address (in addition to event.gfn, which holds the value).
MEM_EVENT_REASON_MSR does not honour the HVMPME_onchangeonly bit,
as doing so would complicate the hvm_msr_write_intercept()
switch-based handling of writes for different MSR addresses,
with little added benefit.

Signed-off-by: Razvan Cojocaru <rzvncj@gmail.com>
Acked-by: Tim Deegan <tim@xen.org>

diff -r c4114a042410 -r 3450c4dfff7f xen/arch/x86/hvm/hvm.c
--- a/xen/arch/x86/hvm/hvm.c	Fri Dec 21 17:05:38 2012 +0000
+++ b/xen/arch/x86/hvm/hvm.c	Thu Jan 03 12:05:13 2013 +0200
@@ -2927,6 +2927,8 @@ int hvm_msr_write_intercept(unsigned int
     hvm_cpuid(1, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
     mtrr = !!(cpuid[3] & cpufeat_mask(X86_FEATURE_MTRR));
 
+    hvm_memory_event_msr(msr, msr_content);
+
     switch ( msr )
     {
     case MSR_EFER:
@@ -3862,6 +3864,7 @@ long do_hvm_op(unsigned long op, XEN_GUE
                 break;
             case HVM_PARAM_MEMORY_EVENT_INT3:
             case HVM_PARAM_MEMORY_EVENT_SINGLE_STEP:
+            case HVM_PARAM_MEMORY_EVENT_MSR:
                 if ( d == current->domain )
                 {
                     rc = -EPERM;
@@ -4485,6 +4488,14 @@ void hvm_memory_event_cr4(unsigned long 
                            value, old, 0, 0);
 }
 
+void hvm_memory_event_msr(unsigned long msr, unsigned long value)
+{
+    hvm_memory_event_traps(current->domain->arch.hvm_domain
+                             .params[HVM_PARAM_MEMORY_EVENT_MSR],
+                           MEM_EVENT_REASON_MSR,
+                           value, ~value, 1, msr);
+}
+
 int hvm_memory_event_int3(unsigned long gla) 
 {
     uint32_t pfec = PFEC_page_present;
diff -r c4114a042410 -r 3450c4dfff7f xen/include/asm-x86/hvm/hvm.h
--- a/xen/include/asm-x86/hvm/hvm.h	Fri Dec 21 17:05:38 2012 +0000
+++ b/xen/include/asm-x86/hvm/hvm.h	Thu Jan 03 12:05:13 2013 +0200
@@ -448,6 +448,7 @@ int hvm_x2apic_msr_write(struct vcpu *v,
 void hvm_memory_event_cr0(unsigned long value, unsigned long old);
 void hvm_memory_event_cr3(unsigned long value, unsigned long old);
 void hvm_memory_event_cr4(unsigned long value, unsigned long old);
+void hvm_memory_event_msr(unsigned long msr, unsigned long value);
 /* Called for current VCPU on int3: returns -1 if no listener */
 int hvm_memory_event_int3(unsigned long gla);
 
diff -r c4114a042410 -r 3450c4dfff7f xen/include/public/hvm/params.h
--- a/xen/include/public/hvm/params.h	Fri Dec 21 17:05:38 2012 +0000
+++ b/xen/include/public/hvm/params.h	Thu Jan 03 12:05:13 2013 +0200
@@ -126,6 +126,7 @@
 #define HVM_PARAM_MEMORY_EVENT_CR4          22
 #define HVM_PARAM_MEMORY_EVENT_INT3         23
 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25
+#define HVM_PARAM_MEMORY_EVENT_MSR          30
 
 #define HVMPME_MODE_MASK       (3 << 0)
 #define HVMPME_mode_disabled   0
@@ -141,6 +142,6 @@
 #define HVM_PARAM_ACCESS_RING_PFN   28
 #define HVM_PARAM_SHARING_RING_PFN  29
 
-#define HVM_NR_PARAMS          30
+#define HVM_NR_PARAMS          31
 
 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
diff -r c4114a042410 -r 3450c4dfff7f xen/include/public/mem_event.h
--- a/xen/include/public/mem_event.h	Fri Dec 21 17:05:38 2012 +0000
+++ b/xen/include/public/mem_event.h	Thu Jan 03 12:05:13 2013 +0200
@@ -45,6 +45,8 @@
 #define MEM_EVENT_REASON_CR4         4    /* CR4 was hit: gfn is CR4 value */
 #define MEM_EVENT_REASON_INT3        5    /* int3 was hit: gla/gfn are RIP */
 #define MEM_EVENT_REASON_SINGLESTEP  6    /* single step was invoked: gla/gfn
are RIP */
+#define MEM_EVENT_REASON_MSR         7    /* MSR was hit: gfn is MSR value, gla
is MSR address;
+                                             does NOT honour
HVMPME_onchangeonly */
 
 typedef struct mem_event_st {
     uint32_t flags;

At 12:05 +0200 on 03 Jan (1357214724), Razvan Cojocaru
wrote:
> Add the new MEM_EVENT_REASON_MSR event type. Works similarly
> to the other register events, except event.gla always contains
> the MSR address (in addition to event.gfn, which holds the value).
> MEM_EVENT_REASON_MSR does not honour the HVMPME_onchangeonly bit,
> as doing so would complicate the hvm_msr_write_intercept()
> switch-based handling of writes for different MSR addresses,
> with little added benefit.
> 
> Signed-off-by: Razvan Cojocaru <rzvncj@gmail.com>
Applied, thanks.

Tim.

> Applied, thanks.
Thank you.

Cheers,
Razvan Cojocaru