similar to: [PATCH] x86: Back port from latest Linux kernel to enable C2/C3 entry via MWAIT

Displaying 20 results from an estimated 10000 matches similar to: "[PATCH] x86: Back port from latest Linux kernel to enable C2/C3 entry via MWAIT"

2008 Oct 30
0
[PATCH 0/3] CPUIDLE: enable C1 FFH
This patchset enable support for C1 mwait entry. [PATCH 1/3] dom0-C1-FFH.patch. It gets C1 information from ACPI table and pass it to Xen. [PATCH 2/3] add-idx-field.patch. This patch adds an idx field in the ''struct acpi_processor_cx''. It can simplify some coding lines. [PATCH 3/3] xen-C1-FFH.patch. It adds support for C1 FFH (mwait) entry. Meanwhile add timing for C1. The
2011 Aug 15
36
expose MWAIT to dom0
There''re basically two methods to enter a given C-state: legacy (hlt + I/O read), and native(using mwait). MWAIT is always preferred when both underlying CPU and OS support, which is a more efficient way to conduct C-state transition. Xen PM relies on Dom0 to parse ACPI Cx/Px information, which involves one step to notify BIOS about a set of capabilities supported by OSPM. One capability
2008 Sep 19
0
[PATCH 0/2] CPUIDLE: fixings for multiple C3 & C2 LAPIC stop
[PATCH 1/2] Support multiple C3 states. There may be multiple ACPI C3 states mapped into different CPU C-states.So made some modification to support this case. [PATCH 2/2] Handle C2 LAPIC timer & TSC stop. ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option ''lapic_timer_c2_ok''
2008 May 05
4
[PATCH] Enable Px/Cx related CPUID/MSR bits for dom0
Enable Px/Cx related CPUID/MSR bits for dom0 to get correct Px/Cx info. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
2011 Mar 13
0
[xen-4.1-testing test] 6412: regressions - FAIL
flight 6412 xen-4.1-testing real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/6412/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-xcpkern-i386-xl-credit2 11 guest-localmigrate fail REGR. vs. 6379 Tests which did not succeed, but are not blocking, including regressions (tests previously passed) regarded as allowable: test-amd64-amd64-win 16
2011 Feb 23
0
[PATCH] Fixing mwait usage when doing cpu offline
Hi, Keir, In debugging the issue "system hang when doing cpu offline", I identified a situation that could cause a dead lock. The scenario is: mwait_idle_with_hint inside play_dead will access per cpu variable, which causes #PF. The #PF handler will use printk, which will schedule a tasklet. In scheduling a tasklet, per cpu variables are needed, otherwise, there will be another #PF.
2012 Nov 02
1
[PATCH] x86/mwait-idle: enable Ivy Bridge Xeon support
Matching a similar change in Linux 3.7-rc. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -365,6 +365,7 @@ static struct intel_idle_id { ICPU(0x2a, snb), ICPU(0x2d, snb), ICPU(0x3a, ivb), + ICPU(0x3e, ivb), {} }; _______________________________________________ Xen-devel mailing list
2010 Mar 09
4
"monitor"-ed address and IPI reduction
What is the point of specifying "current" as the address to monitor? The memory location of interest really is irq_stat[cpu].__softirq_pending, and if that was used it would then also be possible to actually avoid sending IPIs when monitor/mwait are in use, as is being done on Linux. Jan _______________________________________________ Xen-devel mailing list
2008 Sep 19
0
[PATCH 2/2] CPUIDLE: Handle C2 LAPIC timer & TSC stop
ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option ''lapic_timer_c2_ok'' can be used to select simple C2 entry/exit only if the user make sure that LAPIC tmr & TSC will not be stopped during C2. Signed-off-by: Wei Gang <gang.wei@intel.com>
2008 Jul 14
0
[PATCH]PIT broadcast to fix local APIC timer stop issue for Deep C state
Local APIC timer may stop at deep C state (C3/C4...) entry/exit. Initial HPET broadcast working in legacy replacing mode, broke RTC intr, so was bypassed. This patch add the logic that use platform timer (PIT) to reenable local APIC timer at C state entry/exit. Currently, only keep PIT enabled with 100Hz freq. The next step is trying to dynamically enable/disable PIT while needed, and give it
2008 May 20
4
[PATCH] Fix lapic timer stop issue in deep C state
Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this patch add the logic that use platform timer (HPET) to reenable local APIC timer at C state entry/exit. Signed-off-by: Wei Gang <gang.wei@intel.com> Signed-off-by: Yu Ke <ke.yu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com
2012 Mar 01
3
[PATCH v2] x86: Use deep C states for off-lined CPUs
# HG changeset patch # User Boris Ostrovsky <boris.ostrovsky@amd.com> # Date 1330642361 -3600 # Node ID 99df5c6b2964ceaa73651d7bc02fb1ae820f7691 # Parent a7bacdc5449a2f7bb9c35b2a1334b463fe9f29a9 x86: Use deep C states for off-lined CPUs Currently when a core is taken off-line it is placed in C1 state (unless MONITOR/MWAIT is used). This patch allows a core to go to deeper C states
2008 Sep 09
9
[PATCH 2/4] CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast
CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast LAPIC will stop during C3, and resume to work after exit from C3. Considering below case: The LAPIC timer was programmed to expire after 1000us, but CPU enter C3 after 100us and exit C3 at 9xxus. 0us: reprogram_timer(1000us) 100us: entry C3, LAPIC timer stop 9xxus: exit C3 due to unexpected event, LAPIC timer continue running
2012 Apr 24
3
xen acpi cpufreq driver
Hi, i''m not sure if i understood the new acpi xen cpufreq driver - here''s the output when loading xen_acpi_processor module in linux 3.4: dom0 dmesg: [ 32.728151] xen-acpi-processor: (CX): Hypervisor error (-22) for ACPI CPU8 [ 32.728156] xen-acpi-processor: (CX): Hypervisor error (-22) for ACPI CPU9 [ 32.728160] xen-acpi-processor: (CX): Hypervisor error (-22) for
2009 Feb 26
5
[PATCH 4/4] ACPI: Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen
Enable THERM_CONTROL MSR write for dom0 even cpufreq=xen Signed-off-by: Wei Gang <gang.wei@intel.com> diff -r bd683e0397b4 xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Tue Feb 17 22:29:38 2009 +0800 +++ b/xen/arch/x86/traps.c Wed Feb 25 11:23:01 2009 +0800 @@ -2187,10 +2187,17 @@ static int emulate_privileged_op(struct case MSR_IA32_MPERF: case MSR_IA32_APERF:
2002 Apr 29
1
Release of Design library; update of Hmisc library
The Design library has been fully ported to R except for Cox proportional hazards regression modeling (using Therneau's survival package) which will be available in about two weeks. It will take much longer to make all the example code executable, is it currently contains many examples for which data are not provided. Thanks to Xiao Gang Fan <xiao.gang.fan1 at libertysurf.fr> who
2002 Apr 29
1
Release of Design library; update of Hmisc library
The Design library has been fully ported to R except for Cox proportional hazards regression modeling (using Therneau's survival package) which will be available in about two weeks. It will take much longer to make all the example code executable, is it currently contains many examples for which data are not provided. Thanks to Xiao Gang Fan <xiao.gang.fan1 at libertysurf.fr> who
2008 Sep 26
0
[PATCH]CPUIDLE: Initialize timer broadcast mechanism for C2
Without this patch, while running on platforms on which the deepest C-state is C2, acpi_processor_idle fns will call into NULL function. BTW, made a little enhancement for keyhandler print-out to make it more readable. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com
2008 Jul 16
1
[PATCH] Adjust handle_hpet_broadcast to let it run better before broadcast exit
Adjust handle_hpet_broadcast to let it run better before broadcast exit Since hpet_broadcast_exit has been moved after interrupt enabled in C3 case, so adjust the handler of hpet broadcast to adapt to this. Meanwhile, remove a freqently executed debug print line to simplify the serial output. Signed-off-by: Wei Gang <gang.wei@intel.com> diff -r 63317b6c3eab xen/arch/x86/hpet.c ---
2008 Jun 03
0
[PATCH]Improve HPET comparator reprog to prevent intr-near-missing case
HPET intr-near-missing means if the current counter value is too close to the comparator value to be reprogrammed the expected HPET intr may be missing. Linux kernel uses a mininal 48-hpet-ticks(~3.5us) distance to workaround this, but personal observation showed there is still failure case while delta=0xba (~13.5us). So choosing 20us as the MIN_DELTA_NS should be helpful to prevent near-missing