similar to: [PATCH] pit_timer removal when the vmx guest is inactive.

This is an obvious typo. With this patch, checked build of Windows server 2003 can be installed and run on top of VMX domain. Signed-off-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Qing He <qing.he@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Intercepting this MSR is pointless - The swapgs instruction does not cause a vmexit, so the cached result of this is potentially stale after the next guest instruction. It is correctly saved and restored on vcpu context switch. Furthermore, 64bit Windows writes to this MSR on every thread context switch, so interception causes a substantial performance hit. From: Paul Durrant

Currently, Xen does not support injecting an NMI to HVM guest OS. Adding this feature is necessary for those softwares which depend on NMI to function correctly, such as KDB and oprofile. The attached patch allows NMI to be injected to guest OS in NMIP capable platforms. It also enables to queue an NMI and then inject it as soon as possible. Signed-off-by: Haitao Shan

Hi all! Did the nested xen stuff make it into the xen-unstable (4.1-rc1?) tree as suggested back in January by Tim Deegan? TIA ________________________________ Date: Fri, 7 Jan 2011 16:01:12 +0000 From: Tim Deegan <Tim.Deegan@citrix.com> Subject: Re: [Xen-devel] [PATCH 00/12] Nested Virtualization: Overview To: Christoph Egger <Christoph.Egger@amd.com> Cc: Keir Fraser

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

Fix the mistake for debug exception(#DB), overflow exception(#OF; generated by INTO) and int 3(#BP) instruction emulation. For INTn (CD ib), it should use type 4 (software interrupt). For INT3 (CC; NOT CD ib with ib=3) and INTO (CE; NOT CD ib with ib=4), it should use type 6 (software exception). For other exceptions (#DE, #DB, #BR, #UD, #NM, #TS, #NP, #SS, #GP, #PF, #MF, #AC, #MC, and #XM), it

This is to disable SDL repeat key to fix the repeat key issue in slow network connection situation. thx,eddie Signed-off-by: Eddie Dong <eddie.dong@intel.com> diff -r f6fdb6e0d3c9 tools/ioemu/sdl.c --- a/tools/ioemu/sdl.c Thu Nov 17 13:56:50 2005 +++ b/tools/ioemu/sdl.c Sun Nov 27 22:26:07 2005 @@ -592,7 +592,7 @@ sdl_resize(ds, 640, 400); sdl_update_caption(); -

Keir: This is to to make the IDE device model multithreading so that the VMX domain IO access completion (triggering DMA operation) can be asynchronize with the completion of DMA operation. With this patch we get 8%--14% performance gain for kernel build. Thanks, eddie Yang, Xiaowei wrote: > Originally in qemu when a IDE dma transfer is started which is > triggered by access to 0xc000

flight 14916 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/14916/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-amd64-pv 15 guest-stop fail REGR. vs. 14856 test-amd64-i386-xl 14 guest-localmigrate/x10 fail REGR. vs. 14856 test-amd64-i386-xend-winxpsp3 7

From: Yang Zhang <yang.z.zhang@Intel.com> With virtual unrestricted guest feature, L2 guest is allowed to run with PG cleared. Also, allow PAE not set during virtual vmexit emulation. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/hvm.c | 3 ++- xen/arch/x86/hvm/vmx/vvmx.c | 3 +++ 2 files changed, 5 insertions(+), 1 deletions(-) diff --git

> + > +/* The exitcode is in native SVM/VMX format. The forced exitcode > + * is in generic format. > + */ Introducing a 3rd format of exitcode is over-complicated IMO. > +enum nestedhvm_vmexits > +nestedhvm_vcpu_vmexit(struct vcpu *v, struct cpu_user_regs *regs, > + uint64_t exitcode) > +{ I doubt about the necessary of this kind of wrapper. In single layer

import include/asm-ia64/xen/interface.h to introduce introduce definitions necessary for ia64/xen hypercalls. They are basic structures to communicate with xen hypervisor and will be used later. Cc: Robin Holt <holt at sgi.com> Cc: Jeremy Fitzhardinge <jeremy at goop.org> Signed-off-by: Isaku Yamahata <yamahata at valinux.co.jp> Cc: "Luck, Tony" <tony.luck at

import include/asm-ia64/xen/interface.h to introduce introduce definitions necessary for ia64/xen hypercalls. They are basic structures to communicate with xen hypervisor and will be used later. Cc: Robin Holt <holt at sgi.com> Cc: Jeremy Fitzhardinge <jeremy at goop.org> Signed-off-by: Isaku Yamahata <yamahata at valinux.co.jp> Cc: "Luck, Tony" <tony.luck at

This patch fixes MOVS handling memory spanning multiple pages. Signed-off-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com> Thanks, Xiaowei _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Keir: Not sure from when, at least now hvm_do_resume is double invoked in both 1: arch_vmx_do_resume from schedule_tail, and 2) vmx_asm_do_vmentry of ASM code for both x86 32 & 64 bits. I am wondering if the #1 is a redundant, can u have a double check? thx,eddie _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page

Support Alternative Routing-ID Interpretation (ARI), which increases the number of functions that can be supported by a PCIe endpoint. ARI is required by SR-IOV. PCI-SIG ARI specification can be found at http://www.pcisig.com/specifications/pciexpress/specifications/ECN-alt-rid-interpretation-070604.pdf Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong

Support Alternative Routing-ID Interpretation (ARI), which increases the number of functions that can be supported by a PCIe endpoint. ARI is required by SR-IOV. PCI-SIG ARI specification can be found at http://www.pcisig.com/specifications/pciexpress/specifications/ECN-alt-rid-interpretation-070604.pdf Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong

Support Alternative Routing-ID Interpretation (ARI), which increases the number of functions that can be supported by a PCIe endpoint. ARI is required by SR-IOV. PCI-SIG ARI specification can be found at http://www.pcisig.com/specifications/pciexpress/specifications/ECN-alt-rid-interpretation-070604.pdf Signed-off-by: Yu Zhao <yu.zhao at intel.com> Signed-off-by: Eddie Dong <eddie.dong