Displaying 20 results from an estimated 300 matches similar to: "VHDL Implementation?"
2002 Jul 09
1
Vorbis Block Diagram
Hi,
I have looked through the documentation available from the downloads and the
web and haven't yet come across a block diagram which shows exactly how the
process of going from a .wav file to a .ogg file works. I suspect it is the
same as the mp3 process (with a different psychoacoustic model). I found
this document:
2001 Jul 11
1
Hardware Vorbis
There is a 'feeling' on the opencores list that an audio decoder is desired.
(MP3 gets mentioned occasionally, but has its patent problems etc...)
http://www.opencores.org/ no audio projects are underway yet and I think a
vorbis decoder will take a while but even if only a start is made then
others may add to it.
For their one year anniversary they will actually be doing a chip run and
2014 Sep 02
2
[LLVMdev] Python to VHDL using LLVM; was "Re: LLVMdev Digest, Vol 123, Issue 3"
The only VHDL to LLVM project that I know of is nvc. [0] I haven't
tried it personally and from a cursory look through the source it
seems like there is a LLVM backend and a "native" backend (not sure
what that means). If you're really crazy you might want to see if you
could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM
backend for GCC) to get you LLVM IR.
I'm
2011 Oct 07
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Jonas,
>Thanks for your answers.
>
>In one year, I am going to have something like a semester project.
>The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the
2012 Dec 04
1
[LLVMdev] VHDL to promela
To All,
Has anyone worked with generating vhdl code to promela script for the spin model checker??
David Blubaugh
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2008 Jan 25
0
Re: how hard it would be to implement a flac-decoder in VHDL
Quoting flac-dev-request@xiph.org:
> Send Flac-dev mailing list submissions to
> flac-dev@xiph.org
>
> To subscribe or unsubscribe via the World Wide Web, visit
> http://lists.xiph.org/mailman/listinfo/flac-dev
> or, via email, send a message with subject or body 'help' to
> flac-dev-request@xiph.org
>
> You can reach the person managing the list at
>
2011 Oct 06
0
[LLVMdev] LLVM and VHDL simulation
On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote:
> Hi,
>
> I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
> To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis
2011 Oct 06
0
[LLVMdev] TR : LLVM and VHDL simulation
Thanks for your answers.
In one year, I am going to have something like a semester project.
The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL
2011 Oct 02
0
[LLVMdev] LLVM and VHDL simulation
I don't have a solution for you, but when you found one or start the project
on your own, let me know.
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2008 Jan 22
1
Implementing a flac-decoder in VHDL
Hello,
my name is Axel Reimer and I am new to this mailing list. I subscribed
because I was just thinking about how hard it would be to implement a
flac-decoder in VHDL (in order to use it on a Xilinx-FPGA).
Since I am working at a University in Germany I was thinking of offering
this project for students.
What do you think. How much time would you suggest for such an
implementation (if only
2008 Jan 22
0
Re: Implementing a flac-decoder in VHDL
Hello Axel,
I'm an undergraduate student who has been working on a student project
implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca
).
Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I
think that much of this would hold for your students project as well.
The project took significantly longer to complete than we
2011 Oct 10
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
Hi Pavel,
> If you are interested in HDLs perhaps you would be interested in Vlang?
> I am currently working on Verilog fronted and I am looking for somebody with
> VHDL interest to join the Vlang project.
I have never heard about the Vlang project but it seems to be an interesting project. I think I
could be interested to join this project and do the VHDL front-end.
However, there are
2002 Jul 08
1
Vorbis Block Diagram
Hi,
I have looked through the documentation available from the downloads and the
web and haven't yet come across a block diagram which shows exactly how the
process of going from a .wav file to a .ogg file works. I suspect it is the
same as the mp3 process (with a different psychoacoustic model). I found
this document:
2000 Jul 26
5
hardware ogg vorbis decoder
As it seems that the vorbis decoder is now stable with respect to
format/features, would it be time to start thinking about a hardware
implementation?
I would be interested in pursuing this if some there is consensus on
requirements.
If there is some enthusiasm for it then a module could be set up on the
opencores site for a gate-array decoder.
cya, Andrew...
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List
2011 Oct 02
7
[LLVMdev] LLVM and VHDL simulation
Hi,
I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process.
To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This
2007 May 09
2
Next step of Hardware Theora
Hello,
First of all, I would like to say that my work that I wrote in the other
email would be to do in hardware the functions: CopyRecon, LoopFilter and
UpdateUMVBorder. These are modules that Leonardo had made, but it wasn't ok
in FPGA. When I had a chat with Leonardo we were thinking in rewrite these
module for to do this running in FPGA (to debug in a Hardware level is much
more
2007 Mar 22
1
[LLVMdev] Backend: 2 address + 17bit immediate
Hello,
Im (trying) to write a backend for a simple 32bit processor architecture,
with a single instruction format having no condition code registers.
www.docm.mmu.ac.uk/STAFF/A.Nisbet/Sabre.pdf is the short 15 page document
describing the architecture of Sabre. It is a Celoxica developed
research/teaching processor, pages 5-8 contain relevant information for
targetting it from a new compiler
2005 Dec 21
3
Another "Too many files open" post
I'm running Solaris 9 Sparc with Dovecot alpha 5 and using maildir
format.. I noticed in the log file the following error:
dovecot: Dec 20 15:54:18 Error: imap(xxxxxxxx):
open(/export/home/xxxxxxxx/mail/.Sent
Messages/cur/1135013649.002916.mbox:2,Sab) failed: Too many open files
I called the guy and asked him what he was doing... synching his
folders. It hung for a while but finally
2004 Sep 10
3
slow FLAC__file_decoder_seek_absolute()...
Hi,
I checked the archives, but I didn't find anything regarding this
problem. FLAC__file_decoder_seek_absolute takes an incredibly long time
to seek. What can I do about this? How do I fix it?
Here's how I'm calling the function:
if (argc > 2) {
secs = atoi(argv[2]);
seek_point = (FLAC__uint64) secs * sample_rate;
printf("seeking to %d:%02d\n", secs/60,
2013 Aug 30
1
Re: ext3 / ext4 on USB flash drive?
Agh. This is great to have some of this clarified, Ted. It does
unfortunately reinorce my cynicism. But it also fills my heart. That
is, though it might be bad news to hear that I have most likely bought
a piece of crap, and that there's no way I can really tell what's
inside the cover unless either I do some kind of low-level alchemy of
a kind that mere users would normally be well