similar to: Builtin reordered

Hi Teresa, Thank you for the help, adding the "used" attribute worked just fine. It made me realize that the memset function is never inlined by the LTO optimization even without my implementation of the "EmitTargetCodeForMemSet" method. I supposed that the passes dealing with the memset function happen too late, is that correct? Thank you again, Romaric On Fri, Aug 28, 2020

Hi everyone, I'm working in a company to port LLVM on their own processors. I'm try to support several set of instructions and several architectures. I'm using the "--target" options to choose my set of instructions, and I would like to use the "-mcpu" to choose the architecture of which I want to compile the code. Does it seem right? But at the moment I cannot

Hi everyone, I have 2 implementations of "memset". A standard one, and another one optimized when the pointer and the size respect some specific constraints. I am able to choose the proper one in the "EmitTargetCodeForMemSet" method that I implemented for my backend. My issue is when I am compiling with the LTO optimisation, the linker tells me that the optimized memset

Hi all, I'm working in a company to port LLVM on their own processor. I'm trying to run the test-suite, but it seems that it is usually run directly on the processor which is tested. In my case, I cannot run it on the processor, but I have a simulator on which I would like to run the test-suite. Also, it seems to me that the test-suite start by compiling some tools that have to be run

Hello, I have an intrinsic that matches to a asm instruction directly. This intrinsic starts a coprocessor that can do anything. If I put another instruction next to it (a multiplication for example), the "llc" reorders and puts the intrinsic after the multiplication. I have tried all: - Setting the instruction like if it takes 256 cycles or 0 cycles. - Setting the instruction with

Hi, I'm working on OpenCL and I'm using clang as compiler (based on clang 3.7.0). I have a issue, I'm generating a bitcode file (that I can print before before the generation). But when I'm trying to read it again with clang, I have this issue: "error: Invalid record" How can I managed to know where it comes from? Thank you, Romaric Here is what is print before the

Hi all, I'm currently working on implementing ACLE extensions for ARM. There are some memory barrier intrinsics, i.e.__dsb and __isb that require the compiler not to reorder instructions around their corresponding built-in intrinsics(__builtin_arm_dsb, __builtin_arm_isb), including non-memory-access instructions.[1] This is currently not possible. It is sometimes useful to prevent the

Hi,Can I use "reorder" function with barchart as in dotchart? Here are some codes which do not work for me. Thanks Chetty ___________________________ a1c.cast$bmi.cat.reordered[a1c.cast$eth!="Other"] <-with(a1c.cast[a1c.cast$eth!="Other",],reorder(bmi.cat.ordered[a1c.cast$eth!="Other"], BP.FN.RATE,median )) barchart(BP.FN.RATE~

Sorry for probably obvious question but I could not find and answer on mail archive. What would happen to decoded audio quality if the packets fed to decoder are out of order (no jitter buffer)? For example, if order of packets is 0,1,2,4,3,5 (3 and 4 reordered) and there is no FEC. Would it be better, in this case, to drop packet 3 and not decode it at all? Or, if there is FEC, then try to

On 24 June 2014 01:55, Philip Reames <listmail at philipreames.com> wrote: > > On 06/19/2014 09:35 AM, Yi Kong wrote: >> >> Hi all, >> >> I'm currently working on implementing ACLE extensions for ARM. There >> are some memory barrier intrinsics, i.e.__dsb and __isb that require >> the compiler not to reorder instructions around their

Hello all, I want to add a custom intrinsic to the LLVM IR which would be lowered into a pseudo instruction since it doesn't correspond to any real instruction defined by the architecture. The speciality of this intrinsic/pseudo instruction that it should behave like a scheduling barrier: every instruction before the intrinsic has to be emitted before the intrinsic, the same goes for all

Hello all ,  I have a data frame like this  X1X2X3 11815 22916 331017 441118 551219 661320 771421 now i want to randomly reorder the variable X2  but the row element should be same  as for example  X1X2X3 12916 251219 331017 471421 561320 61815 741118 how can i do that ?? Hint :  this could be helpful :  if X2 is only a vector like this  X2<-c(8,9,10,11,12,13,14) so i can easily reorder

Chris Lattner wrote: > On Fri, 19 Dec 2003, Yueqiang wrote: > > >>In high level languge there are usually have time and sync instruction, >>to handle async and sync operation. >>I want to know how LLVM take an count of these. > > > I'm not sure exactly what 'time' and 'sync' operations you're talking > about, or what languages

Hi Tim, Thank you a lot for your reply. So IIUC, optimization passes in opt do not reorder IR instructions, only passes in llc that move MIR instructions around. Is it correct? On the back-end (llc) side, hasSideEffects might prevent some reordering. But I just learn about TargetInstrInfo::isSchedulingBoundary. Can you tell me what are the differences between the two please? Thank you very much

Hello, at the recent EuroLLVM developer meeting in Bristol I held a BoF session on the topic "Towards implementing #pragma STDC FENV_ACCESS". I've also had a number of follow-on discussions both on-site in Bristol and online since. This post is intended as a summary of my current understanding set of requirements and implementation details covering the overall topic. I'm

This intrinsic seems very ill-defined, apparently it can be freely reordered and does _not_ act like a compiler barrier. [1] Other than source compatibility, why would one want this intrinsic? What semantics is it supposed to give? [1] < http://connect.microsoft.com/VisualStudio/feedback/details/691456/-readeflags-intrinsic-can-be-reordered-by-the-compiler > On Tue, Dec 17, 2013 at 11:00

Hi Ulrich, I am interested in knowing if the current proposals also take into account the FP_CONTRACT pragma and the ability to implement options that imply a specific value for the FLT_EVAL_METHOD macro. Additionally, I am not aware of the IR being able to represent the potentially deferred loss of precision that the C language semantics provide; in particular, applying such semantics to the

On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others. Thanks for the note - excellent point. Looking at

On 19.03.2016 16:25, Mehdi Amini wrote: > Hi, > > Can you elaborate what is the impact at the IR level? > If the point is just about how you lower for you target, why are you needing an IR level attribute? You backend if free to specialize the lowering for any intrinsic regardless the IR level attributes. As I explained in my reply to Philip, what I really need is a way to get

On 05/23/2018 11:06 AM, Hubert Tong via llvm-dev wrote: > Hi Ulrich, > > I am interested in knowing if the current proposals also take into > account the FP_CONTRACT pragma We should already do this (we turn relevant operations into the @llvm.fmuladd. when FP_CONTRACT is set to on during IR generation). > and the ability to implement options that imply a specific value for >