similar to: [LLVMdev] VHDL to promela

The only VHDL to LLVM project that I know of is nvc. [0] I haven't tried it personally and from a cursory look through the source it seems like there is a LLVM backend and a "native" backend (not sure what that means). If you're really crazy you might want to see if you could massage GHDL [1] (VHDL GCC frontend) + DragonEgg [2] (LLVM backend for GCC) to get you LLVM IR. I'm

Hi, I am using PinaVM which is a prototype of a SystemC front-end based on "LLVM". The only version that it works with is 2.8. Also to test PinaVM, we need llvm-g++ (I think clang does not work). However, when I want to run an example, i get the following error, which i think is related to llvm-g++: reza at RezaUbuntu:~/pinavm-pinavm/systemc-examples/jerome-chain$ make promela

The issue here (even if you get dragonegg working) is that the thing that most newer linuxes install when you apt-get llvm-gcc isn't actually llvm-gcc, it's gcc with the dragonegg plugin. Even if the plugin issues are sorted out, the "fake" llvm-gcc doesn't support -emit-llvm so this wouldn't work. You'll probably need to pull a 2.8 of it from llvm.org or a

Hi, I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis is not a list of assembly instructions but a description of a circuit with logical gates. This

On Sun, Oct 2, 2011 at 4:24 PM, Baggett Jonas <Jonas.Baggett at hefr.ch> wrote: > Hi, > > I am wondering if someone knows about a VHDL simulator (maybe still in early developpement) that use LLVM in its compilation process. > To summarize, VHDL is a hardware description language, which means that VHDL is like any other programming language except that the output of its synthesis

Reza Sheykhi <hajishey at msu.edu> writes: > I got the following answers: > > which perl > /usr/bin/perl > > which llvm-config > /usr/local/bin/llvm-config > > which llvm-as > /usr/local/bin/llvm-as > > /usr/bin/llvm-confing --version > bash: /usr/bin/llvm-confing: No such file or directory Uh, there is a typo on the command above, it should be

I got the following answers: which perl /usr/bin/perl which llvm-config /usr/local/bin/llvm-config which llvm-as /usr/local/bin/llvm-as /usr/bin/llvm-confing --version bash: /usr/bin/llvm-confing: No such file or directory /usr/local/bin/llvm-config --version 2.8 Quoting Óscar Fuentes <ofv at wanadoo.es>: > Reza Sheykhi <hajishey at msu.edu> writes: > >> Thank you

I don't have a solution for you, but when you found one or start the project on your own, let me know. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111002/f54dd8de/attachment.html>

Hello, my name is Axel Reimer and I am new to this mailing list. I subscribed because I was just thinking about how hard it would be to implement a flac-decoder in VHDL (in order to use it on a Xilinx-FPGA). Since I am working at a University in Germany I was thinking of offering this project for students. What do you think. How much time would you suggest for such an implementation (if only

I'm currently looking to start my working on my major project for College. I want to create an audio CD archival/ playback server. There will be a base server and also several satellite players. I will be building a secondary server for my car. And in the car power is at a premium so I wanted true hardware support (unlike phatnoise which is software based). The car will support both

Hi Jonas, >Thanks for your answers. > >In one year, I am going to have something like a semester project. >The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the

Quoting flac-dev-request@xiph.org: > Send Flac-dev mailing list submissions to > flac-dev@xiph.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.xiph.org/mailman/listinfo/flac-dev > or, via email, send a message with subject or body 'help' to > flac-dev-request@xiph.org > > You can reach the person managing the list at >

Thanks for your answers. In one year, I am going to have something like a semester project. The idea I have for this project would be to create (for simulation only) a VHDL front-end to LLVM, compile some VHDL code with the newly created compilator and also with a commercial compilator and simulator and compare the performance of both simulations. I won't have the time to do a full VHDL

Hello Axel, I'm an undergraduate student who has been working on a student project implementing a project like this for our Fourth Year Design Symposium (http://eceprojects.uwaterloo.ca ). Our VHDL decoder is targeting an Altera FPGA (Cyclone II), however I think that much of this would hold for your students project as well. The project took significantly longer to complete than we

Hi Pavel, > If you are interested in HDLs perhaps you would be interested in Vlang? > I am currently working on Verilog fronted and I am looking for somebody with > VHDL interest to join the Vlang project. I have never heard about the Vlang project but it seems to be an interesting project. I think I could be interested to join this project and do the VHDL front-end. However, there are

Hi, I've had problem with a program using LLVM that tried to dynamic_cast objects created in the JIT execution engine, from the native part of the program (for the curious, the program is PinaVM http://gitorious.org/pinavm/pages/Home). I've narrowed down the issue to the linkage of weak_odr and linkonce_odr symbols, used for the vtables, and that _must_ be unique for dynamic_cast to

On 30.8.2011, at 19.19, Eli Friedman wrote: > reg2mem won't do quite this transformation... not sure exactly what you need. I need to get rid of phis. This code is compiled from C++ and for some functions there are no phis, but multiple call instructions. I am targeting hardware in the end, and the next tool reading the IR does not like phis when it's generating VHDL. My questions may

Hi, For the synthesis backend which translate to VHDL or Verilog, I don't know if I will use LLVM. It will depend on how easy it is to play with concurrent statements with LLVM. For the simulation I will use LLVM because I can anyways artificially make the compiled code sequencial. It would allow me to benefit from all the nice things from LLVM like existing optimisations. I have never

Hey! I was wondering if active-HDL (VHDL simulator) will work with WINE 1.0? active-HDL (i regret to say) is only for windows.... :( Thanks :)

Hi all, the CallGraph pass is only available in opt. Is there any substantial reason for that? Or is it only because it seems not to be useful for llc? I want to use it in an backend that is derived from the CBackend. I need the information what functions are called in every other function to build communication struktures between the functions. The backend is generating VHDL from C code.