Displaying 20 results from an estimated 20000 matches similar to: "[LLVMdev] What does promote elements do ?"
2012 Jul 05
3
[LLVMdev] Vector argument passing abi for ARM ?
Hi Rotem,
Thanks for the quick answer, how do I know which type is legal/illegal with respect to calling convention ?
Best Regards
Seb
> -----Original Message-----
> From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
> Sent: Thursday, July 05, 2012 11:21 AM
> To: Sebastien DELDON-GNB; llvmdev at cs.uiuc.edu
> Subject: RE: Vector argument passing abi for ARM ?
>
> The
2012 Jul 05
2
[LLVMdev] RE : Vector argument passing abi for ARM ?
Hi Duncan,
I also thought it was a bug, especially since it worked with LLVM 3.0, but since it is not defined by ABI, I was not sure if I need to submit it as a BUG.
I wanted to be sure that it is an actual BUG before submitting it and got the not-a-bug answer.
Here is a small example to reproduce the problem I'm experiencing:
; ModuleID = 'bugparam.ll'
target datalayout =
2012 Jul 05
0
[LLVMdev] Vector argument passing abi for ARM ?
Hi Sebastien,
> Thanks for the quick answer, how do I know which type is legal/illegal with respect to calling convention ?
the code generators are supposed to produce working code no matter what the
parameter type is. The fact that the ARM ABI doesn't specify how <2 x i8>
is passed just means that the code generators can pass it using whatever
technique it feels like (since it
2011 Oct 08
4
[LLVMdev] LLC ARM Backend maintainer
Hi Tanya,
The new type-legalization mode (-promote-elements) which enables vector-select in LLVM (and a nice perf boost for several workloads), is currently disabled because of a _single_ bug in the ARM codegen which makes a few tests fail. If ARM is not a supported target, can I mark these tests as 'XFAIL' and enable vector-select support in LLVM ?
Thanks,
Nadav
-----Original
2012 Jul 05
0
[LLVMdev] RE : Vector argument passing abi for ARM ?
Hi Sebastien,
> I also thought it was a bug, especially since it worked with LLVM 3.0, but since it is not defined by ABI, I was not sure if I need to submit it as a BUG.
yes it is a bug.
> I wanted to be sure that it is an actual BUG before submitting it and got the not-a-bug answer.
I didn't read Nadav's reply as saying there was no bug, in fact he explicitly
said in his email
2012 Jul 05
2
[LLVMdev] Vector argument passing abi for ARM ?
Hi all,
I was wondering if there is a defined ABI for passing vector as parameter for ARM target.
For instance is this valid to write .ll statement like:
; ModuleID = 'bugconv.ll'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "thumbv7-none-linux-androideabi"
define
2012 Jun 25
2
[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?
Hi Anton,
You're right it fails with a different message with llc 3.0.
Anyway thanks for your help.
Best Regards
Seb
> -----Original Message-----
> From: Anton Korobeynikov [mailto:anton at korobeynikov.info]
> Sent: Monday, June 25, 2012 3:39 PM
> To: Sebastien DELDON-GNB
> Cc: LLVMdev at cs.uiuc.edu; Rotem, Nadav
> Subject: Re: RE : [LLVMdev] Is llc broken for Cortex-A9
2012 Jun 25
2
[LLVMdev] RE : Is llc broken for Cortex-A9 + neon ?
Hi Anton & Nadav,
I filled this problem a while ago here http://llvm.org/bugs/show_bug.cgi?id=13111
Thinking it first was an LLVM opt bug. Shall I assign it to Nadav or create a new one ?
Seb
________________________________________
De : Anton Korobeynikov [anton at korobeynikov.info]
Date d'envoi : lundi 25 juin 2012 15:31
À : Sebastien DELDON-GNB
Cc : LLVMdev at cs.uiuc.edu; Rotem,
2012 Jul 05
0
[LLVMdev] Vector argument passing abi for ARM ?
The argument passing calling convention is undefined for illegal types, such as <2 x i8>. The invalid misaligned loads on ARM sounds like a bug in the ARM backend.
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Sebastien DELDON-GNB
Sent: Thursday, July 05, 2012 12:14
To: llvmdev at cs.uiuc.edu
Subject: [LLVMdev] Vector
2012 Sep 21
2
[LLVMdev] RE : Question about LLVM NEON intrinsics
Hi Eli,
Thanks for the answer, it clarifies the situation for me. Do you know if there is Pass in LLVM that could be adapted to 'legalize' intrinsics calls ?
Or shall I define my own intrinsics for non supported types ?
Best Regards
Seb
________________________________________
De : Eli Friedman [eli.friedman at gmail.com]
Date d'envoi : vendredi 21 septembre 2012 11:54
À : Sebastien
2012 Sep 21
0
[LLVMdev] Question about LLVM NEON intrinsics
On Sep 21, 2012, at 2:58 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote:
> Hi Eli,
>
> Thanks for the answer, it clarifies the situation for me. Do you know if there is Pass in LLVM that could be adapted to 'legalize' intrinsics calls ?
> Or shall I define my own intrinsics for non supported types ?
You should never generate these sorts of intrinsics with
2012 Sep 21
5
[LLVMdev] Question about LLVM NEON intrinsics
Hi all,
I would like to know if LLVM Neon intrinsics are designed to support only 'Legal' types for NEON units.
Using llc -march=arm -mcpu=cortex-a9 vmax4.ll -o vmax4.s on following ll code:
; ModuleID = 'vmax.ll'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple =
2012 Jul 27
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x i8>, <2 x i16> or <4 x i8>. The problem is that there are no vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.
This can be reproduced by setting in
2012 Jul 31
3
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Ahh yep, thanks for catching that, new patch attached.
> -----Original Message-----
> From: Hal Finkel [mailto:hfinkel at anl.gov]
> Sent: Tuesday, July 31, 2012 1:40 PM
> To: Villmow, Micah
> Cc: Developers Mailing List
> Subject: Re: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
>
> Micah,
>
> I think that your patch is missing the necessary
2012 Aug 01
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Micah,
One more thing ;) -- llvm::getEnumName
in utils/TableGen/CodeGenTarget.cpp
-Hal
On Tue, 31 Jul 2012 21:02:02 +0000
"Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> Ahh yep, thanks for catching that, new patch attached.
>
> > -----Original Message-----
> > From: Hal Finkel [mailto:hfinkel at anl.gov]
> > Sent: Tuesday, July 31, 2012 1:40 PM
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
No, that is correct. I am adding the new types so that I can bitcast v2i8 into a v1i16 and then perform the 'and' operation and have legalize types turn the v1i16 into a scalar.
Though I am having trouble in understanding how x86 supports the <1 x i64> type. Based on looking at the code, it should fail because v1i64 is not supported on the x86 platform as far as I can tell.
Micah
2012 Jul 30
4
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Sorry, <4 x i8> should convert to a <1 x i32>. What currently is happening is that it is returning a <2 x i32> because <1 x i32> does not exist.
Micah
> -----Original Message-----
> From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
> Sent: Monday, July 30, 2012 10:51 AM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
Hrmm.... PromoteVectorOp doesn't seem to follow this at all.
http://llvm.org/svn/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
EVT VT =
2012 Jul 30
0
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
I don't know how your target architecture looks like, but I suspect that <4 x i8> should not be legalized to <1 x i32>. I think that what you are seeing is that <4 x i8> is first split into <2 x i8>, and later promoted to <2 x i32>. At the moment different targets can only affect type-legalization by declaring different legal types. A number of us discussed the
2012 Jul 30
2
[LLVMdev] Vector promotion broken for <2 x [i8|i16]>
v4i8 itself is a legal type, just not on the 'AND' operation.
So there seems to be multiple problems here.
1) PromoteVectorOp doesn't handle the case where the types are not the same size, this occurs because #2
2) getTypeToPromoteTo doesn't actual check to see if the type it should promote to makes any sense.
3) PromoteVectorOp also doesn't handle the case where