similar to: [LLVMdev] [PATCH] Apply Thumb2 ROR optimization only when Thumb2 is supported

Hi Matt, You're absolutely right, that pattern should definitely have an "only-in-Thumb2" predicate attached. Do you have commit access? Also, if you have a reduced test case, that would be awesome, but the patch is correct as-is even if not. -Jim On Jul 2, 2012, at 8:05 AM, Matt Fischer <mattfischer84 at gmail.com> wrote: > I've been playing around with using LLVM

I've been playing around with using LLVM on one of our projects, which runs on an arm1176jzf-s processor. When compiling for Thumb, a couple of the generated assembly files end up with a 'ror.w' instruction, which is a Thumb2 instruction. Since arm1176jzf-s doesn't support Thumb2, the assembler then turns around and barfs on it. I don't have any experience with this

I went ahead and committed it, along with a basic test case, in svn r159538. On Jul 2, 2012, at 9:34 AM, Jim Grosbach <grosbach at apple.com> wrote: > Hi Matt, > > You're absolutely right, that pattern should definitely have an "only-in-Thumb2" predicate attached. > > Do you have commit access? Also, if you have a reduced test case, that would be awesome, but

Hello everyone, I've added the "S" suffixed versions of ARM and Thumb2 instructions to the rest of those declared in tablegen. For example, "movs" or "muls". Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr r1, r2, r3 ----> orrs r1, r2, r3 cmp r1, 0 This optimization has

Hello everyone, I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Besides, I propose the codegen optimization based on them, which removes the redundant comparison in patterns like orr

Hello everyone, I've added suffixed versions of ARM and Thumb2 instructions to tablegen. That is, for example, "movs" or "orrs". I implemented a rather simple codegen optimization which removes the comparison in patterns like orr r1, r2 ---> orrs r1, r2 cmp r1, 0 It works and have already shown nice acceleration (e.g., 3.3% in SQLite). I have a few

On Feb 17, 2011, at 10:35 PM, Вадим Марковцев wrote: > Hello everyone, > > I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls". > Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched. Adding separate "s" instructions is

Hi Karel, It actually looks like the argument parser has parsed "thumb -mattr=v7,thumb2,vfp3" as the full argument to "-march=". Strange. The easiest way to get what you want is probably "-mtriple thumbv7--". v7 has Thumb2 enabled and VFPv3 (along with NEON) by default. Cheers, James ________________________________________ From: llvmdev-bounces at cs.uiuc.edu

Hello, I'm trying to convince llc to compile into thumb2 ISA on ARMv7. I'm using: -march=thumb -mattr=v7,thumb2,vfp3 but llc complains about this with: llc: error: invalid target 'thumb -mattr=v7,thumb2,vfp3' I'm using LLVM from Aug 29 2011. To me the set of options looks sane so I'd like to ask what's wrong with this. Thanks! Karel

On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: > Hi Everybody, > > I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > > > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c > > and get error message: > >

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent:

Sure. Use legal ARM mode syntax for the instruction. Specifically, there is no offset immediate for the ARM mode LDREX instruction. It's illegal syntax to supply one, even if it's zero. -Jim On Aug 16, 2012, at 2:36 PM, Lei Zhao <leizhao833 at gmail.com> wrote: > It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is

Hi Everybody, I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c and get error message: ------------------------------------------------------- main.c:9:9: error: instruction requires: thumb2 "ldrex

It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is there a way to make it compile to regular arm mode? Thanks. - Lei On Aug 16, 2012, at 4:00 PM, Eli Friedman wrote: > On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: >> Hi Everybody, >> >> I recently did a cross-compiling

On Jul 27, 2012, at 9:04 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > Hi all, > > Does llc –march=thumb –mcpu=cortex-a9 enable generation of thumb2 code for armv7 ? That's how I usually do it. Somewhere in the target description we associate a9 with -mattr=+thumb2. There are plenty of other ways to get the same result, and it's all very confusing and

Hi, after perusing through llc -debug output and stepping through the ARMGenDAGIsel.inc in the debugger, I would greatly like some help in tracking down a failing match to a pattern I specified: First, here is a snippet of a successful match (done in ARM mode) ISEL: Starting pattern match on root node: 0x1e7adf0: i32,ch = load 0x1e4c030, 0x1e78210, 0x1e78310<LD4[ConstantPool]> [ID=10]

Hi all, Does llc -march=thumb -mcpu=cortex-a9 enable generation of thumb2 code for armv7 ? Best Regards Seb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120727/da758ea0/attachment.html>

Hi Damjan, > This sounds like a dead end as newer binutils are GPLv3. Unfortunately, you have to live with this. Until recently binutils were quite buggy wrt thumb2 code, so, most probably you will need new binutils in any case. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

On 22 June 2011 19:18, Anton Korobeynikov <anton at korobeynikov.info> wrote: > Unfortunately, you have to live with this. Until recently binutils > were quite buggy wrt thumb2 code, so, most probably you will need new > binutils in any case. Hi Anton, It's not so simple. GPL3 can be quite a nuisance to change and even to use. This is why LLVM is becoming to popular for ARM...

The thumb2 instructions include unsigned and signed divide. Attached are a patch and test routine. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.diff URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/675cf4c5/attachment.ksh> -------------- next part -------------- An embedded and charset-unspecified text was