Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Question about porting LLVM - code selection without assembler feature"
2011 Jan 24
0
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Lu Mitnick <king19880326 at gmail.com> writes:
> Hello all,
>
> I am adding a new target into LLVM. However there is a assembler for
> that target and I just want LLVM to generate assembly. I read the
> document "Writing an LLVM Backend". I am wondering to know whether I
> can ignore the Inst field in the following example:
I'm not an expert here so I'll
2011 Jan 24
1
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Hello David,
Thanks for your example. Is that means that DAG pattern is consist of LLVM
IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b,
CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR
instruction of "set" in "LLVM Language Reference Manual". Is that correspond
to $dst = op $b, $c?? Would you mind to tell me whether there is
2014 Jun 07
3
[LLVMdev] Load/Store Instruction Error
Hi all,
I started to write an LLVM backend for custom CPU. I created XXXInstrInfo
but there are some problems. I searched for it but I couldn't find
anything. Can anyone help me?
include "XXXInstrFormats.td"
def simm16 : Operand<i32> {
let DecoderMethod = "DecodeSimm16";
}
def mem : Operand<i32> {
let PrintMethod = "printMemOperand";
let
2011 Nov 08
0
[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?
I'm a bit confused as to how some of the values in a Sparc store
instruction actually come to be set. The Sparc backend defines a store as:
def STri : F3_2<3, 0b000100,
(outs), (ins MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>;
F3_2 and it's superclasses are defined as follows:
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> : // ...
This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what you mean.
2012 Jul 05
2
[LLVMdev] bug in tablegen?
I think that what I did originally should have worked and the bug was
correct as I reported it.
Here is an alternate implementation which has the same problem.
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
!cast<FRRR16_ins>(I).OutOperandList,
!cast<FRRR16_ins>(I).InOperandList,
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean.
I.OutOperandList == (outs CPU16Regs:$rx)
I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
On 07/02/2012 09:26 PM, Sean Silva wrote:
> I think you're missing the template args for `FRRR16_ins` in the first
> argument. The switch in TGParser::ParseType() doesn't cover the case
> of types with template args though... which makes me wonder what is
2012 Jul 03
2
[LLVMdev] bug in tablegen?
I've filed the following bug. Maybe I'm doing something stupid here or
maybe someone knows of a workaround.
The following fragment from mips16 (not yet checked into main source).
The problem is that I should be able to pass parameters:
I.OutOperandList, I.InOperandList
But instead, I must back substitute what I know the values of these are.
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry,
2012 Jul 05
0
[LLVMdev] bug in tablegen?
This variant works:
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
// !cast<FRRR16_ins>(I).OutOperandList,
// !cast<FRRR16_ins>(I).InOperandList,
!cast<FRRR16_ins>(I).AsmString,
[(set CPU16Regs:$rx,
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace =
2012 Jul 03
0
[LLVMdev] bug in tablegen?
I think you're missing the template args for `FRRR16_ins` in the first
argument. The switch in TGParser::ParseType() doesn't cover the case
of types with template args though... which makes me wonder what is
going on inside of TableGen to make `I.f` and `I.AsmString` valid...
--Sean Silva
On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote:
> I've filed
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,
2013 Mar 24
5
[LLVMdev] Types in TableGen instruction selection patterns
I have updated TableGen to support a new format for instruction selection patterns.
Before:
def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
After:
def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
I'm not at the machine that has the changes, but it was failing at index 0.
Micah
From: Owen Anderson [mailto:resistor at mac.com]
Sent: Thursday, April 19, 2012 3:35 PM
To: Villmow, Micah
Cc: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Micah,
I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate?
-Owen
On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> I am trying to make
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.
2008 Oct 28
1
[LLVMdev] Accessing InstrFormat.td fields
When I setup my InstrFormat fields, I added some custom fields specific
for my backend. How do I access these from inside LLVM?
For example:
class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMD";
dag OutOperandList = outs;
dag InOperandList = ins;
let Pattern = pattern;
let
2011 Nov 20
0
[LLVMdev] How can I output assembly comments from emitPrologue()?
So, an update. I have managed to generate comments, although it does create
a non-existent instruction. My method is as follows (and I would appreciate
any comments on how to do it "better", although note that this won't make
it into the final code :).)
1. I declared a "fake" instruction type to hold comments, ala:
class FakeInst<dag outs, dag ins, string asmstr,
2013 Mar 25
0
[LLVMdev] Types in TableGen instruction selection patterns
Jakob Stoklund Olesen wrote:
> I have updated TableGen to support a new format for instruction selection patterns.
>
> Before:
>
> def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
>
> After:
>
> def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
>
> Since the pattern matching happens on a DAG with type labels, not
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Sun, 1 Oct 2006, Roman Levenstein wrote:
> I'm trying to implement a new backend for an embedded CISC processor.
> Therefore I thought that it makes sense to take X86 target as a basis,
> to save some time.
Ok. Note that the X86 backend is one of the most complex though, because
it supports several subtargets and ABIs, which makes it more complex than
some other targets.
>