similar to: [LLVMdev] pseudo instructions

Hi, LLVMer. I use pseudo-instructions ADJCALLSTACK(DOWN | UP) to adjust call stacks, and it works well with "-O0" option. However, ADJCALLSTACK(DOWN | UP) are removed during codegen DCE pass under "-O2". What have I ignored? Thanks. -- 杨勇勇 (Yang Yong-Yong) -------------- next part -------------- An HTML attachment was scrubbed... URL:

You should set them as using/defining your stack register with : let Defs = [STACKREG], Uses = [STACKREG] in { __ YOUR INSTRUCTION __ } Marcello On 04/09/13 07:56, 杨勇勇 wrote: > I use pseudo-instructions ADJCALLSTACK(DOWN | UP) to adjust call > stacks, and it works well with "-O0" option. However, > ADJCALLSTACK(DOWN | UP) are removed during codegen DCE pass under

Hello, I'm trying to add pseudo 64-bit load and store instructions for AArch64, which should have latencies set to "1" while being otherwise exactly the same as normal load and store instructions. Various assertions fire (even different ones for the same binary, maybe something is uninitialized) and I can't understand what's wrong. Related pieces added by me: to

Hi Jim, thank you for the quick response. I have used InstAlias in some cases, but these are really simple pseudo instructions where the pseudo instruction is more like a special case of existing one, like using fixed operand or simply a more human understandable way of presenting an operation. I know that there are predicates available to improve matching, but can InstAlias use conditions to

Hi Vladimir, The pass you refer to isn't used by the assembler at all. That's strictly a compiler codegen thing. The assembler equivalents are expressed via InstAlias constructions. Again, though, those are for a single output instruction, so you need something more. Sprecifically, you can handle assembly pseudo-instructions in C++ code. Something like the ARM assembler's

Reed, Have a look at custom inserters. In particular, how they're used for atomics in the ARM backend. -Jim On Feb 17, 2013, at 12:51 PM, Reed Kotler <rkotler at mips.com> wrote: > After discussions last night, I'm leaning towards going legit with all my pseudo expansions in Mips 16. > > Some I think I can clearly do by just putting in the proper side effects of

Hi Renato, > > I'm trying to add pseudo 64-bit load and store instructions for AArch64, which > > should have latencies set to "1" while being otherwise exactly the same as > > normal load and store instructions. > > Can I ask why would you need that? This is the only way I found to stop Machine Instruction Scheduler from reordering load and store

Hello, Im back trying to finish my backend to a simple RISC cpu SABRE now that most of the tedious process of examining undergraduate students is out of the way. I have managed to describe the registers and the instructions in the architecture and have added support for 32 bit immediates (thanks to Christopher Lamb) as the instruction set only supports 17 bit immediates directly. Could

Hi all, I'm trying to solve a problem that we have in implementation of the assembler for Mips platform in llvm. Mips has some pseudo instructions that, depending on the arguments can be emitted as one or more real instructions by the assembler. For example load immediate instruction can have multiple expansions depending on a size of immediate operand: This expansion is for 0 ≤ j ≤ 65535. li

On 2 Mar 2018, at 11:09, Nagaraju Mekala via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am working on a target which requires to generated two > instructions for a single branch instruction. > ex: > imm 1 > br r4,0xabcd > branch address is 0x1abcd, imm has the upper 16 bits and br has > lower 16 bits. > > Can anyone let me know how to write

What happens is that a SPLIT operation is part of the spill node, and as a pseudo op, the instruction gets erased after processing its first def. However the later defs still need to refer to it, so instead delay spilling until after that whole RA node is done processing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79462 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc:

This is the old MIPS I code that sort of does what I need to do. This seems really involved to do such a simple thing. Maybe there are now helper classes for this or some better example I can look at. I suppose I can mimick this if people say this just the correct way to do this in LLVM. static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,

Some stuff did not get pasted in properly. static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, DebugLoc dl, const MipsSubtarget *Subtarget, const TargetInstrInfo *TII, bool isFPCmp, unsigned Opc) { //

Howdy, <---stuff deleted -----> Basically the architecture I want to compile to (SABRE) RISC does not support a conditional branch or a select instruction. It supports explicit branches of the form. blt %a, %b, imm // branch on less than iff %a < %b then pc = pc + imm So there are various branch instructions like .... ble, beq, bne, blt, bltu and bleu (unsigned) Im just

Sounds like bundles will be the simplest to start with though I suppose I could just lower the pseudos after scheduling is done; for now. Bundles will prevent things from being able to be scheduled in more creative ways but for that I need to think more about the problem. So I can just create a bundle, insert instructions in it, and all will work more or less? I'm trying to take the next

MachineRegisterInfo is maintaining a list of live-out registers for the MachineFunction. It contains the return value registers, and is typically created by XXXISelLowering::LowerReturn(). Various passes after instruction selection need to look at this list to determine which physical registers are live in return blocks. Eventually, the register allocators copy these live-out registers onto the

Hi, I'm having problems when trying to JIT IR generated from C++ with clang. My code resides in a dynamically loaded shared object, and crashes when I call getPointerToFunction, claiming that it encountered a pseudo instruction. Interestingly, a very similar code that run as a separate executable JITing the same IR works fine. Note that I have not have modified LLVM. Any suggestions what

For anyone encountering this problem in the future, the cause of this problem was debugging symbols (-g) given to clang when generating IR. On 20/05/2012 12:21, "Weiss, Eran" <Eran.Weiss at emc.com> wrote: >Hi, > >I'm having problems when trying to JIT IR generated from C++ with clang. >My code resides in a dynamically loaded shared object, and crashes when I

>> Do the ARM usages include allowing a single pseudo-instruction to expand >> to multiple real instructions? For example, a movw/movt pair? If so, I’m >> *very* opposed to that part. > > > Why? For people writing assembly manually, having pseudo instructions to > encapsulate common patterns is very useful. Would it be acceptable for this pseudo-instruction to

On Tue, Oct 29, 2013 at 1:21 PM, Jim Grosbach <grosbach at apple.com> wrote: > > On Oct 26, 2013, at 5:02 PM, Chris Lattner <clattner at apple.com> wrote: > > On Oct 25, 2013, at 5:22 PM, Sean Silva <chisophugis at gmail.com> wrote: > > I’m not sure macros are a good analogy, but there are other >> pseudo-instructions that we’re not always able to