similar to: [LLVMdev] Thumb categorizing TST wrongly

Displaying 20 results from an estimated 300 matches similar to: "[LLVMdev] Thumb categorizing TST wrongly"

2010 Sep 14
0
[LLVMdev] Thumb categorizing TST wrongly
On Sep 14, 2010, at 12:09 PM, Gabor Greif wrote: > I see strangeness on Thumb TST (tTST) predicate 'isCompare' > > It is true for regular ARM, false for Thumb: > > (gdb) p MI->dump() > TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR<imp-def>; GPR:% > reg16397 > $24 = void > (gdb) p MI->getDesc().isCompare() > $25 = true > > > (gdb)
2010 Sep 15
0
[LLVMdev] LLVMdev Digest, Vol 75, Issue 32
2010/9/15 <llvmdev-request at cs.uiuc.edu> > Send LLVMdev mailing list submissions to > llvmdev at cs.uiuc.edu > > To subscribe or unsubscribe via the World Wide Web, visit > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > or, via email, send a message with subject or body 'help' to > llvmdev-request at cs.uiuc.edu > > You can
2010 Sep 21
0
[LLVMdev] inline asm constraints examples/tests
On Sep 21, 2010, at 2:45 PMPDT, John Thompson wrote: > fatal error: error in backend: Ran out of registers during register allocation! > Please check your inline asm statement for invalid constraints: > INLINEASM <es:>, 0, 10, %reg16396<def>, 10, %reg16397<def>, 10, %reg16398<def>, 10, %reg16399<def>, 10, %reg16400<def>, 10, %reg16401<def>,10,
2010 Sep 21
3
[LLVMdev] inline asm constraints examples/tests
Dale, Sorry, I see you did say I should run the gcc tests. I apologize for forgetting this. I'll work on getting them to run here. Chris et. all, I have a fix for the assertion failure in the enclosed llvmmultalt8.patch file. I didn't realize the input constraints could have different numbers of alternatives from the outputs, which now makes sense. The pr20314-2.c file now compiles
2010 Nov 08
2
[LLVMdev] [LLVMDev] Register Allocation and copy instructions
Hi, while writing my register allocator, I have come across a case which confuses me because the llvm definition cannot be mapped to machine code. For instance I come across (1) and I reduce it to (2). However a copy instruction cannot move from EDX to CX. What mechanics in LLVM will tell me that I cannot make this move during register allocation, or how can I tell from (1) that I cannot execute
2014 Apr 22
2
[LLVMdev] where is F7 opcode for TEST instruction on X86?
hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in
2010 Sep 21
0
[LLVMdev] inline asm constraints examples/tests
On Sep 20, 2010, at 9:40 PMPDT, John Thompson wrote: > Thanks, Stuart. Sorry, I had some left-over editing cruft in my email. From Googling runtest, I had found dejagnu, which I'd heard some folks were using over there, so I used the local package manager to install it. But from what you said I went ahead and got the dejagnu sources and built it, but had problems in running make
2016 Mar 09
2
[CodeGen] PeepholeOptimizer: optimizing condition dependent instrunctions
Hi, I find it's quite strange how condition dependent instructions are processed in PeepholeOptimizer::runOnMachineFunction: 01577 if ((isUncoalescableCopy(*MI) && 01578 optimizeUncoalescableCopy(MI, LocalMIs)) || 01579 (MI->isCompare() && optimizeCmpInstr(MI, &MBB)) || 01580 (MI->isSelect() && optimizeSelect(MI,
2010 Sep 21
4
[LLVMdev] inline asm constraints examples/tests
Thanks, Stuart. Sorry, I had some left-over editing cruft in my email. >From Googling runtest, I had found dejagnu, which I'd heard some folks were using over there, so I used the local package manager to install it. But from what you said I went ahead and got the dejagnu sources and built it, but had problems in running make install, which is trying to put it /usr/local/bin rather than
2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to
2018 Jul 10
2
Stuck with instruction in tablegen
Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&
2016 Mar 10
2
[CodeGen] PeepholeOptimizer: optimizing condition dependent instrunctions
Hi Quentin, Yes, the code allows to process connected instructions. Although it should be taken into account that the instruction next to the current processed instruction must never be erased because this invalidates iterator. I've been fixing a bug in AArch64InstrInfo::optimizeCompareInstr: instructions are converted into S form but it's not checked that they produce the same flags as
2018 Jul 10
2
Stuck with instruction in tablegen
2007 Sep 03
1
how to tst my backup mail server
Dear ALl, Sorry for my posting here but do apprecite if u guys help me.. I have already CenOS 5 and been used as my Primary DNS and primary sendmail mail server and is working perfectly fine i also have another Centos MAchine being used as my secondary DNS server and been workin fine.. i want to use this machine as my backup mail server and has gone to the DOCS have configured DNS and
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
Hi, Compiling attached test-case, which is reduced version of of uECC_shared_secret from tinycrypt library [1], with --target=arm-linux-gnueabi -march=armv6-m -Oz -S results in reloading of register holding function's address before every call to blx: ldr r3, .LCPI0_0 blx r3 mov r0, r6 mov r1, r5 mov r2, r4 ldr r3,
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
Hi, I have attached WIP patch for adding foldMemoryOperand to Thumb1InstrInfo. For the following case: void f(int x, int y, int z) { void bar(int, int, int); bar(x, y, z); bar(x, z, y); bar(y, x, z); bar(y, y, x); } it calls foldMemoryOperand twice, and thus converts two calls from blx to bl. callMI->dump() shows the function name "bar" correctly, however in generated
2019 Nov 21
2
[ARM] Peephole optimization ( instructions tst + add )
Hello! I noticed that in some cases clang generates sequence of AND+TST instructions: For example: AND x3, x2, x1 TST x2, x1 I think these instructions should be merged to one: ANDS x3, x2, x1 ( because TST <Xn>, <Xm> is alias for ANDS XZR, <Xn>, <Xm> -
2009 Aug 11
1
Categorizing Lines
Hi all, i have a dataset of 3D coordinates and can't figure out how to' tell R which One Are the individuals: I have 3 columns which i named x,y and z And then i have 2607 Lines, but each specimen is 33 Lines (79 specimens) How can i tell R to' categorize individuals every 33 Lines? Thanks in advance
2019 Apr 14
2
[A bug?] Failed to use BuildMI to add R7 - R12 registers for tADDi8 and tPUSH of ARM
Hi Craig, Thanks for the information. Can you point to the source that specifies tGPR to be R0 - R7? I tried to search in ARMInstrThumb.td but couldn’t find it. Thanks, - Jie On Apr 14, 2019, at 15:28, Craig Topper <craig.topper at gmail.com<mailto:craig.topper at gmail.com>> wrote: I believe there is probably a separate instruction in LLVM for thumb2 add. Probably starting with t2